A ultra-high speed DAC apparatus (e.g., with a full sampling frequency not less than 20 GHz) may include one or more digital pre-coders and DAC modules. Each DAC module may include multiple current-mode DAC systems and a first power combiner. The gate length of transistors within each DAC module may be between 6 and 40 nm. Each current-mode DAC system includes a transmission line (e.g., 40 to 80 microns long) coupled to multiple interleaving sub-DAC systems (within the current-mode DAC systems) and the first power combiner. The first power combiner combines, without interleaving, analog signals that have been interleaved within the current-mode DAC systems. The impedance of the first power combiner matches the impedance of each of the current-mode DAC systems and a load of the first power combiner. A second power combiner combines, without interleaving, analog signals from the DAC modules.

A variable gain phase shifter includes an I/Q generator and a vector summation circuit. The I/Q generator generates phase signals based on an input signal. The vector summation circuit adjusts magnitudes and directions of first, second, third and fourth in-phase vectors and first, second, third and fourth quadrature vectors, and generates an output signal by summing the in-phase vectors and the quadrature vectors, based on the phase signals, selection signals and current control signals. The vector summation circuit includes first, second, third and fourth vector summation cells and first, second, third and fourth current control circuits. The first and second vector summation cells adjust the directions of the first and second in-phase vectors and the first and second quadrature vectors. The third and fourth vector summation cells adjust the directions of the third and fourth in-phase vectors and the third and fourth quadrature vectors. The first and second current control circuits are connected to the first and second vector summation cells, and adjust an amount of a first current and an amount of a second current. The third and fourth current control circuits are connected to the third and fourth vector summation cells, and adjust an amount of a third current and an amount of a fourth current.

Multipliers and Multiply-Accumulate (MAC) circuits are fundamental building blocks in signal processing, including in emerging applications such as machine learning (ML) and artificial intelligence (AI) that predominantly utilize digital-mode multipliers and MACs. Generally, digital multipliers and MACs can operate at high speed with high resolution, and synchronously. As the resolution and speed of digital multipliers and MACs increase, generally the dynamic power consumption and chip size of digital implementations increases substantially that makes them impractical for some ML and AI segments, including in portable, mobile, near edge, or near sensor applications. The multipliers and MACs utilizing the disclosed current mode data-converters are manufacturable in main-stream digital CMOS process, and they can have medium to high resolutions, capable of low power consumptions, having low sensitivity to power supply and temperature variations, as well as operating asynchronously, which makes them suitable for high-volume, low cost, and low power ML and AI applications.

A digital-to-analog converter circuit is provided. The digital-to-analog converter circuit includes one or more digital-to-analog converter cells. A first digital-to-analog converter cell includes a first transistor which is configured to be switched to a conductive state when the first digital-to-analog converter cell is activated. A first terminal of the first transistor is coupled to a defined potential, wherein a second terminal of the first transistor is coupled to a common output node of the one or more digital-to-analog converter cells. The digital-to-analog converter circuit further includes a voltage protection circuit coupled between the common output node of the one or more digital-to-analog converter cells and an output node of the digital-to-analog converter circuit to regulate a voltage between the common output node and the defined potential.

A current digital-to-analog converter includes a binary current-generating section configured to generate a binary-weighted current based on a first set of control signals; a unary current-generating section configured to generate a unary-weighted current based on a second set of control signals; and a current combining circuit configured to add or subtract a reference current and a current generated by a current source of the unary current-generating section using the binary-weighted current.

A digital to analog converter (DAC) that receives a binary coded signal and generates an analog output signal includes a binary-to-thermometer decoder and a resistive network. The decoder receives the binary coded signal, and decodes it into thermometer signals. The resistive network has branches that are coupled to an output terminal of the DAC in response to the thermometer signals. Each of the branches includes first and second resistors, and a switch. The first resistor is coupled between a first reference voltage and the switch, and the second resistor is coupled between a second reference voltage and the switch. The switch couples either the first resistor or the second resistor to the output terminal in response to a corresponding thermometer signal.

A ultra-high speed DAC apparatus (e.g., with a full sampling frequency not less than 20 GHz) may include one or more digital pre-coders and DAC modules. Each DAC module may include multiple current-mode DAC systems and a first power combiner. The gate length of transistors within each DAC module may be between 6 and 40 nm. Each current-mode DAC system includes a transmission line (e.g., 40 to 80 microns long) coupled to multiple interleaving sub-DAC systems (within the current-mode DAC systems) and the first power combiner. The first power combiner combines, without interleaving, analog signals that have been interleaved within the current-mode DAC systems. The impedance of the first power combiner matches the impedance of each of the current-mode DAC systems and a load of the first power combiner. A second power combiner combines, without interleaving, analog signals from the DAC modules.

In certain aspects, an analog-to-digital converter includes a first capacitive digital-to-analog converter (DAC), a second capacitive DAC, and a comparator including a first input, a second input, and an output. The analog-to-digital converter also includes a switch circuit including a first input coupled to the first capacitive DAC, a second input coupled to the second capacitive DAC, a first output coupled to the first input of the comparator, and a second output coupled to the second input of the comparator. The analog-to-digital converter further includes a first switch coupled between the output of the comparator and the first input of the comparator, and a successive approximation register (SAR) coupled to the output of the comparator, the first capacitive DAC, and the second capacitive DAC.

Included are a loop filter, a quantization circuit section, and a current steering digital-analog conversion section. The quantization circuit section converts a loop filter output into a digital value. The current steering digital-analog conversion section is provided in a feedback loop that feeds back the output of the quantization circuit section to the loop filter. Then, each of the analog-digital converters includes a first input signal current path, a second input signal current path, a first feedback current path, and a second feedback current path. The first input signal current path feeds a first input signal current to an input end of a first stage integrator of the loop filter. The second input signal current path feeds a second input signal current, a current opposite in sign to the first input signal current, to an input end of a second stage integrator of the loop filter. The first feedback current path connects one feedback output end of the current steering digital-analog conversion section to the input end of the first stage integrator of the loop filter. The second feedback current path connects other feedback output end of the current steering digital-analog conversion section to the input end of the second stage integrator of the loop filter.

A hybrid digital-to-analog converter (DAC) driver circuit includes a current-mode DAC driver, a voltage-mode DAC driver, and a combination circuit. The current-mode DAC driver may be configured to receive a first set of bits of a digital input signal and to generate a first analog signal. The voltage-mode DAC driver may be configured to receive a second set of bits of the digital input signal and to generate a second analog signal. The combination circuit may be configured to combine the first analog signal and the second analog signal and to generate an analog output signal. The DAC driver circuit may be terminated by adjusting resistor values of the voltage-mode DAC driver. The current-mode DAC driver and the voltage-mode DAC driver are differential drivers, and may be configured to operate with a single clock signal.