Increasing a dynamic range of a digital to analog converter (DAC). A signal analysis element is positioned prior to the DAC in a processing path. The element evaluates an instantaneous amplitude of a signal to be applied to the DAC. The DAC is capable of a first full scale value. An additional current source supports a second full scale value of the DAC, which is greater than the first full scale value. Upon the element determining that a condition is not satisfied, the element employs current steering to couple the additional current source to a current sink. However, upon the element determining that the condition is satisfied, the element employs current steering to couple the additional current source to an output of the DAC to support the second full scale value of the DAC.

A coarse tuning synthesizer for wireless communication includes a digital control unit, a digital-to-analog converter, and a comparator. The digital control unit includes an output node coupled to a first input node of a VCO (voltage controlled oscillator). The digital-to-analog converter includes a first node coupled to the first input node of the VCO. The comparator includes an output node coupled to an input node of the digital control unit. The comparator also includes a first input node coupled to a second node of the digital-to-analog converter and a second input node coupled to an output node of the VCO.

A variable gain phase shifter includes an I/Q generator and a vector summation circuit. The I/Q generator generates phase signals based on an input signal. The vector summation circuit adjusts magnitudes and directions of first, second, third and fourth in-phase vectors and first, second, third and fourth quadrature vectors, and generates an output signal by summing the in-phase vectors and the quadrature vectors, based on the phase signals, selection signals and current control signals. The vector summation circuit includes first, second, third and fourth vector summation cells and first, second, third and fourth current control circuits. The first and second vector summation cells adjust the directions of the first and second in-phase vectors and the first and second quadrature vectors. The third and fourth vector summation cells adjust the directions of the third and fourth in-phase vectors and the third and fourth quadrature vectors. The first and second current control circuits are connected to the first and second vector summation cells, and adjust an amount of a first current and an amount of a second current. The third and fourth current control circuits are connected to the third and fourth vector summation cells, and adjust an amount of a third current and an amount of a fourth current.

A ultra-high speed DAC apparatus (e.g., with a full sampling frequency not less than 20 GHz) may include one or more digital pre-coders and DAC modules. Each DAC module may include multiple current-mode DAC systems and a first power combiner. The gate length of transistors within each DAC module may be between 6 and 40 nm. Each current-mode DAC system includes a transmission line (e.g., 40 to 80 microns long) coupled to multiple interleaving sub-DAC systems (within the current-mode DAC systems) and the first power combiner. The first power combiner combines, without interleaving, analog signals that have been interleaved within the current-mode DAC systems. The impedance of the first power combiner matches the impedance of each of the current-mode DAC systems and a load of the first power combiner. A second power combiner combines, without interleaving, analog signals from the DAC modules.

A circuit for digital-to-analog conversion using a plurality of 3-level cells includes a circuit for digital-to-analog conversion using a plurality of 3-level cells mutually independently providing positive electricity, providing negative electricity, or floating. The circuit including a preprocess circuit and a shift circuit. The preprocess circuit is configured to receive thermometer code data generated from signed binary data and generate a shift count for shifting a cell pointer pointing to one of the plurality of 3-level cells for dynamic element matching (DEM) from the thermometer code data. The shift circuit is configured to store the cell pointer and shift the stored cell pointer according to the shift count. The shifted cell pointer is shifted in proportion to an absolute value of the binary data in a direction depending on a sign of the binary data.

A differential amplifier circuit includes: a control current source supplying a control current; paired bipolar transistors; an a variable resistance circuit including: a series circuit of a first resistor and a second resistor having an identical resistance, the series circuit electrically connected between a first terminal and a second terminal of the variable resistance circuit; a first field effect transistor (FET) having a source and a drain being electrically connected to emitters of the paired bipolar transistors, respectively; and a second FET having a drain, a gate being electrically connected to the drain thereof, the gate of the first FET, and a control terminal of variable resistance circuit, a source being electrically connected to a connection node between the first resistor and the second resistor, wherein the control current source adjusts the control current to allow transconductance of the second FET to be kept constant.

A class-D amplifier includes an analog-to-digital converter (ADC) configured to generate a first digital signal based on an analog input signal and a feedback signal received at an input node. A loop filter is configured to modify the first digital signal by moving an error of the ADC out of a predetermined frequency band, and a compensation filter is configured to further modify the first digital signal by introducing one or more poles or zeros, thereby generating a second digital signal. An output circuit is configured to generate an output signal at an output node based on the second digital signal, and the feedback signal is generated from the output signal.

A wideband, frequency agile, radio frequency digital-to-analog converter (RF-DAC) based phase modulator includes first, second, and third RF-DACs, each configured to upconvert an input I/Q digital baseband signal pair to a local oscillator (LO) frequency but with the first RF-DAC being driven by a first set of LO clocks, the second RF-DAC being driven by a second set of LO clocks that is forty-five degrees out of phase with respect to the first set of LO clocks, and the third RF-DAC being driven by a third set of LO clocks that is a further forty-five degrees out of phase with respect to the second set of LO clocks. First, second, and third upconverted analog signals produced by the first, second, and third RF-DACs are combined to reinforce the fundamental LO component while canceling 3.sup.rd-order and 5.sup.th-order LO harmonics.

A hybrid digital-to-analog converter (DAC) driver circuit includes a current-mode DAC driver, a voltage-mode DAC driver, and a combination circuit. The current-mode DAC driver may be configured to receive a first set of bits of a digital input signal and to generate a first analog signal. The voltage-mode DAC driver may be configured to receive a second set of bits of the digital input signal and to generate a second analog signal. The combination circuit may be configured to combine the first analog signal and the second analog signal and to generate an analog output signal. The DAC driver circuit may be terminated by adjusting resistor values of the voltage-mode DAC driver. The current-mode DAC driver and the voltage-mode DAC driver are differential drivers, and may be configured to operate with a single clock signal.

A current digital-to-analog converter includes a binary current-generating section configured to generate a binary-weighted current based on a first set of control signals; a unary current-generating section configured to generate a unary-weighted current based on a second set of control signals; and a current combining circuit configured to add or subtract a reference current and a current generated by a current source of the unary current-generating section using the binary-weighted current.