An electronic control unit includes a pair of D/A conversion circuits, which performs D/A conversion processing of a pair of digital data and outputs a pair of analog signals. Each of the pair of D/A conversion circuits performs the D/A conversion processing by splitting input digital data into more-significant digital data and less-significant digital data. More-significant D/A conversion part performs analog conversion processing in accordance with the more-significant digital data by using an element string circuit, which outputs split voltages by splitting predetermined reference voltages. The more-significant conversion circuits output a maximum value and a minimum value in absolute voltage ranges, which are different from each other, in accordance with the more-significant digital data. Less-significant conversion parts perform analog conversion processing in accordance with less-significant digital data by using the maximum value and the minimum value of the different absolute voltage ranges, which are outputted from the more-significant D/A conversion parts, as reference voltages. The element string circuit is shared by the pair of D/A conversion circuits.

The systems and methods discussed herein utilized a wireless or wired transceiver having a transmitter and a receiver. The transceiver is configured to reduce distortion contributions associated with echo cancelling. The transmitter provides a replica signal and a transmit signal. The replica signal and the transmit signal can be provided using a common switch.

A digital-to-analog conversion circuit, a data driver including the same, and a display device are provided. The circuit includes: a reference voltage generation part, generating a reference voltage group having different voltage values; a decoder, selecting and outputting multiple reference voltages with overlapping from the reference voltage group based on the digital data signal; an amplification circuit, where m (m being an integer of 1 or more and less than x) of first to x.sup.th input terminals respectively receive m of multiple reference voltages, and, as an output voltage, a voltage amplified by averaging the voltages respectively received by the first to x.sup.th input terminals with predetermined weighting ratios is output; and a selector, which, in a first selection state, supplies the output voltage to (x-m) input terminals among the first to x.sup.th input terminals, and in a second selection state, supplies the reference voltages to the (x-m) input terminals.

A digital-to-analog conversion circuit, a data driver including the same, and a display device are provided. The circuit includes: a reference voltage generation part, generating a reference voltage group having different voltage values; a decoder, selecting and outputting multiple reference voltages with overlapping from the reference voltage group based on the digital data signal; an amplification circuit, where m (m being an integer of 1 or more and less than x) of first to x.sup.th input terminals respectively receive m of multiple reference voltages, and, as an output voltage, a voltage amplified by averaging the voltages respectively received by the first to x.sup.th input terminals with predetermined weighting ratios is output; and a selector, which, in a first selection state, supplies the output voltage to (x-m) input terminals among the first to x.sup.th input terminals, and in a second selection state, supplies the reference voltages to the (x-m) input terminals.

A level shifter, a digital-to-analog converter (DAC), and a buffer amplifier, and a source driver and an electronic device including the same are provided. The source driver includes a level shifter configured to receive digital bits and provide a level-shifted output signal; a DAC including a resistor string configured to provide a plurality of gradation voltages formed by an upper limit voltage and a lower limit voltage being received through one end and the other end, and an N-type metal oxide semiconductor (NMOS) switch and a P-type MOS (PMOS) switch configured to be controlled by the level-shifted output signal and output a gradation voltage corresponding to the level-shifted output signal; and an amplifier configured to amplify a signal provided by the digital-to-analog converter, and the lower limit voltage is provided to a body electrode of the NMOS switch.

A semiconductor device in which variations are controlled is provided. The semiconductor device has a function of converting a digital signal into an analog signal, and includes a digital-analog converter circuit, an amplifier circuit, first to fourth switches, a first output terminal, a second output terminal, and a power source. The amplifier circuit is configured to perform feedback control when the first switch and the fourth switch are on and the second switch and the third switch are off. The amplifier circuit is configured to perform comparison control when the first switch and the fourth switch are off and the second switch and the third switch are on; utilizing this, variations in the digital-analog converter circuit and the amplifier circuit are controlled.

Provided is a current output circuit 1 including a pseudo sine wave separation circuit 11 that separates a pseudo sine wave represented by a digital code Din into two pseudo half-waves represented by digital signals D1 and D2, a DA converter 113 that converts the pseudo half-wave represented by the digital signal D1 into an analog half-wave signal V1, a DA converter 114 that converts the pseudo half-wave represented by the digital signal D2 into an analog half-wave signal V2, and a voltage-current conversion circuit 12 that converts voltages of the half-wave signals V1 and V2 into currents and outputs a current Iout obtained by combining the currents.

A switched-capacitor amplifier includes a sampling capacitor, a first switch, a differential amplifier, a reference power supply, a second switch, a third switch, and a controller configured to execute on and off control of the first to third switches. The second switch includes a series circuit of first and second metal oxide semiconductor (MOS) transistors and a potential holding capacitor connected between a node that is a common connection point of the first and second MOS transistors and a ground.

An apparatus includes a digital-to-analog converter coupled in series with a source follower, wherein the digital-to-analog converter is configured to control a current flowing through the source follower, and an amplifier having a first input coupled to a reference generator, a second input coupled to a common node of the source follower and the digital-to-analog converter, and an output coupled to a gate of the source follower.

A voltage ladder is used to generate reference voltages. The voltage ladder is used by multiple digital-to-analog converters (DACs). In particular, the voltage ladder is used by multiple pulse-width modulation (PWM) DACs. Having multiple DACs utilize a common voltage ladder for their reference voltages reduces mismatched output voltages between DACs. Having multiple DACs utilize the common voltage ladder helps ensure that the reference voltages used by different DACs are not affected by process, voltage, and/or temperature variations in the reference voltages that would occur when using different voltage ladders for each DAC.