A capacitor-based digital-to-analog-converter produces a level-shifted analog outputs by precharging respective sets of output-generating capacitors to different applied potentials and then floating a common output of the sets of capacitors such that charge is redistributed among the capacitors through the common output to yield, across all the capacitors, a uniform precharge voltage that falls between the different applied potentials.

A semiconductor device includes first and second terminals, a reference resister being coupled between the first and second terminals, third and fourth terminals, a sensor resister being coupled between the third and fourth terminals, a first buffer which supplies a first reference voltage to the first terminal, a second buffer which supplies a second reference voltage to the fourth terminal, a reference voltage generation circuit which supplies one of first and second voltages alternately in a time division manner as the first reference voltage and supplies the other as the second reference voltage, a first analog-to-digital conversion circuit which performs analog-to-digital conversion on a signal line coupled to the third terminal, an RC filter disposed on the signal line, a noise detector which detects noise of the signal line, wherein a time constant of the RC filter is changed based on a result of the noise detector.

A digital-to-analog conversion circuit (60) for converting a digital input sequence to an analog representation is disclosed. It comprises a first DAC, (100) wherein the first DAC (100) is of a capacitive voltage division type having a capacitive load (110). Furthermore, it comprises a second DAC (120) having a resistive load (130). An output (104) of the first DAC (100) and an output (124) of the second DAC (120) are connected, such that said capacitive load (110) and said resistive load (130) are connected in parallel.

A stage, suitable for use in an analog to digital converter or a digital to analog converter, can have a plurality of slices that can be operated together to form a composite output. The stage can have reduced thermal noise, while each slice on its own has sufficiently small capacitance to respond quickly to changes in digital codes applied to the slice. This feature allows a fast conversion to be achieved without loss of noise performance.

The present disclosure addresses a concept for capacitor scaling. A first capacitor is provided with a first signal capacitance between a first electrode and a second electrode of the first capacitor and with a first parasitic capacitance between the first capacitor's first electrode and AC ground. A sum of the first signal capacitance and the first parasitic capacitance yields a first total capacitance. A second capacitor is provided with a second signal capacitance between a first electrode and a second electrode of the second capacitor and with a second parasitic capacitance between the second capacitor's first electrode and AC ground. A sum of the second signal capacitance and the second parasitic capacitance yields a second total capacitance. While the first signal capacitance differs from the second signal capacitance, the first total capacitance equals the second total capacitance.

A capacitor-based digital-to-analog-converter produces a level-shifted analog outputs by precharging respective sets of output-generating capacitors to different applied potentials and then floating a common output of the sets of capacitors such that charge is redistributed among the capacitors through the common output to yield, across all the capacitors, a uniform precharge voltage that falls between the different applied potentials.

Arrangement for controlling micromechanical actuators, including a digital-to-analog converter and a plurality of micromechanical actuators; wherein the micromechanical actuators are coupled to a connecting structure; wherein the digital-to-analog converter is configured to provide a voltage to be applied to the connecting structure by an adjustable capacitive voltage division that is dependent on a digital input value of the digital-to-analog converter, wherein the digital-to-analog converter is configured to directly include a capacitance of the connecting structure in the capacitive voltage division.

The present disclosure relates to a compensation circuit for compensating for an offset voltage that is present in an output signal output by a force sensor. The compensation circuit comprises: voltage divider circuitry, the voltage divider circuitry configured to receive a bias voltage that is also supplied to the force sensor and to output a control voltage derived from the bias voltage, wherein a component mismatch ratio of the voltage divider circuitry is adjustable to correspond to a component mismatch ratio of the force sensor; current generator circuitry configured to receive the control voltage and to generate a compensating current based on the received control voltage; and amplifier circuitry configured to receive the differential signal output by the force sensor and the compensating current and to output a compensated differential output signal in which the offset voltage is at least partially cancelled.

The present disclosure provides digital to analog conversion circuitry comprising: a set of input nodes for receiving a digital input code; an output node for outputting an analog output signal representative of the input code; and a plurality of selectable conversion elements, wherein a parameter of each of the plurality of selectable conversion elements is configured such that a transfer function between the input code and the output analog signal is non-monotonic.

A time-interleaved noise-shaping successive-approximation analog-to-digital converter (TI NS-SAR ADC) is shown. A first successive-approximation channel has a first set of successive-approximation registers, and a first coarse comparator operative to coarsely adjust the first set of successive-approximation registers. A second successive-approximation channel has a second set of successive-approximation registers, and a second coarse comparator operative to coarsely adjust the second set of successive-approximation registers. A fine comparator is provided to finely adjust the first set of successive-approximation registers and the second set of successive-approximation registers alternately. A noise-shaping circuit is provided to sample residues of the first and second successive-approximation channels for the fine comparator to finely adjust the first and second sets of successive-approximation registers.