According to at least one aspect, a delta sigma modulator circuit is provided. The delta sigma modulator circuit includes a first signal processor circuit configured to receive an input signal and a feedback signal and generate a processed signal using the input signal and the feedback signal, a quantizer configured to generate a digital code using the processed signal, a second signal processor circuit configured to receive the digital code, segment the digital code to form a segmented digital code that is smaller in size than the digital code, and generate a rotated digital code using the segmented digital code at least in part by rotating the segmented digital code to compensate for an excess loop delay in the circuit, and an digital-to-analog converter (DAC) configured to receive the rotated digital code and generate the feedback signal using the rotated digital code.

A sigma delta modulator includes a sigma delta modulating loop and a plurality of adjusting loops. The sigma delta modulating loop processes an input signal and an adjustment signal based on a first clock signal, so as to generate a quantized output signal. The first clock signal has a clock cycle. The sigma delta modulating loop has a first delay time that is the same as M times of the clock cycle. M is an integral multiple of 0.5 and is larger than 1. The adjusting loops delay the quantized output signal for second delay times, respectively, so as to generate the adjustment signal.

Certain aspects of the present disclosure provide methods and apparatus for implementing sampling rate scaling of an excess loop delay (ELD)-compensated continuous-time delta-sigma modulator (CTDSM) analog-to-digital converter (ADC). One example ADC generally includes a loop filter; a quantizer having an input coupled to an output of the loop filter; one or more digital-to-analog converters (DACs), each having an input coupled to an output of the quantizer, an output coupled to an input of the loop filter, and a data latch comprising a clock input for the DAC coupled to a clock input for the ADC; and a clock delay circuit having an input coupled to the clock input for the ADC and an output coupled to a clock input for the quantizer.

A delta-sigma modulator. The delta-sigma modulator includes a loop filter (LF) and a digital-to-analog converter (DAC) connected to an input of the LF. The delta-sigma modulator also includes an asynchronous successive-approximation register (ASAR) quantizer (QTZ) connected to the DAC. The delta-sigma modulator also includes a second order noise coupling circuit (NC) connected to the ASAR and the DAC.

Circuits for compensating delta-sigma modulators for excess loop delay are described. These circuits may be coupled to quantizers, and may configured to select the threshold values supplied to the quantizers for comparison with an analog signal. The threshold values may each be selected from a corresponding plurality of reference values, and may be set such that the numerical order of threshold values varies over time. For example, the threshold value provided to a first comparator of the quantizer may be greater than the threshold value provided to a second comparator of the quantizer in a first time interval, but the opposite scenario may occur in a second time interval. The circuits may include multiplexers for selecting the threshold values, thermometric encoders, reference selectors and reference multiplexers.

A sigma delta modulator includes a sigma delta modulating loop and a plurality of adjusting loops. The sigma delta modulating loop processes an input signal and an adjustment signal based on a first clock signal, so as to generate a quantized output signal. The first clock signal has a clock cycle. The sigma delta modulating loop has a first delay time that is the same as M times of the clock cycle. M is an integral multiple of 0.5 and is larger than 1. The adjusting loops delay the quantized output signal for second delay times, respectively, so as to generate the adjustment signal.

The purpose of the present invention is to provide a high-power-efficiency and low-design-cost transmission device by implementing, with a constant clock, delta-sigma modulation maintaining a zero current switching property in an amplifier. This delta-sigma modulator comprises: a pulse phase signal generation unit for generating a pulse phase signal from a phase signal; a delta-sigma modulation unit for generating a pulse amplitude signal obtained by delta-sigma modulating an amplitude signal with a constant clock; a phase sorting unit for outputting a control signal on the basis of the phase signal; a delay switching unit for delaying the pulse amplitude signal on the basis of the control signal; and a mixing unit for outputting a pulse string obtained by multiplying together the delayed pulse amplitude signal and the pulse phase signal.

An exemplary quantizer includes a multi-bit analog-to-digital converter (ADC) and a first digital-to-analog converter (DAC) feedback circuit. The multi-bit ADC has an internal DAC associated with comparison of each sampled analog input of the multi-bit ADC. The multi-bit ADC converts a currently-sampled analog input into a first digital output. A first noise-shaped truncation output is derived from the first digital output. The first DAC feedback circuit transfers a first truncation residue associated with the first noise-shaped truncation output to the internal DAC. The transferred first truncation residue is reflected in comparison of a later-sampled analog input of the multi-bit ADC via the internal DAC.

According to at least one aspect, a delta sigma modulator circuit is provided. The delta sigma modulator circuit includes a first signal processor circuit configured to receive an input signal and a feedback signal and generate a processed signal using the input signal and the feedback signal, a quantizer configured to generate a digital code using the processed signal, a second signal processor circuit configured to receive the digital code, segment the digital code to form a segmented digital code that is smaller in size than the digital code, and generate a rotated digital code using the segmented digital code at least in part by rotating the segmented digital code to compensate for an excess loop delay in the circuit, and an digital-to-analog converter (DAC) configured to receive the rotated digital code and generate the feedback signal using the rotated digital code.

A signal processing circuit has a first signal loop with a first signal processing block and a first feedback path that extends around the first signal processing block, the first signal processing block having a frequency dependence that causes the first signal loop to generate a passband. A second signal processing block is downstream of the first signal loop. A second feedback path extends from downstream of the second signal processing block to upstream of the first signal processing block. In operation, the first feedback path reinforces a signal in the passband and the second feedback path conditions the signal at an output downstream of the first signal processing block.