Asynchronous electrical circuitry produces a stationary carrier signal and encodes a system input signal amplitude into output signal time-sequence information by establishing at a digitizer an operating point value as an average amplitude of the system input signal. It applies to the digitizer a multicomponent digitizer-input signal corresponding to a sum of a passband signal component and a feedback signal component to produce a pulse-width modulated digitizer output signal representing the system input signal. An asynchronous time delay is introduced to produce the pulse-width modulated system output signal. The circuitry performs digital-to-analog conversion (DAC) to the pulse-width modulated system output signal to produce a DAC output signal. The DAC output signal or its summation with the passband signal component is integrated to produce the feedback signal component. Additional, multiple-order embodiments include sequential feedback paths or carrier-shaping functions.

A continuous-time sigma-delta modulator includes a VCO-based quantizer, a rotator, a truncation circuit and a digital-to-analog converter (DAC). The VCO-based quantizer is arranged to generate a thermometer code based on an input signal and a feedback signal. The rotator is coupled to the VCO-based quantizer, and is arranged to generate a phase-shifted thermometer code based on the thermometer code and a phase shift, and generate a rearranged thermometer code based on the phase-shifted thermometer code to comply with a specific pattern. The truncation circuit is coupled to the rotator, and is arranged to extract a most significant bit (MSB) part from the rearranged thermometer code. The DAC is coupled to the truncation circuit, and is arranged to generate the feedback signal according to at least the MSB part. Two alternative continuous-time sigma-delta modulators are also disclosed.

System and methods for input path matching in pipelined continuous-time Analog-to Digital Converters (ADCs), including pipelined Continuous-Time Delta Sigma Modulator (CTDSM) based ADCs, includes an input delay circuit disposed in a continuous-time input path from an input of an analog input signal to a first summing circuit of the continuous-time ADC. At least one digital delay line is disposed between an output of an earlier stage sub-ADC (of a plurality of pipelined sub-ADCs) and a sub-digital-to-analog converter (DAC) that is coupled to the first summing circuit, and between the earlier stage sub-ADC and a digital noise cancellation filter. The digital delay line(s) is configured to enable calibration of delay of output of the earlier stage sub-ADC provided to the sub-DAC and the digital noise cancellation filter in accordance with process variations of the input delay match circuit to minimize residue output at first summing circuit.

Asynchronous electrical circuitry (400, 500, 600, 700, 800, 900) produces a stationary carrier signal (470, 470) and encodes a system input signal (460, 460) amplitude into output signal time-sequence information by establishing at a digitizer (410, 510, 610, 710, 810, 910) an operating point value (416, 516, 616, 716, 816, 916) as an average amplitude of the system input signal. It applies to the digitizer a multicomponent digitizer-input signal (470, 470) corresponding to a sum of a passband signal component and a feedback signal component to produce a pulse-width modulated digitizer output signal (480, 480) representing the system input signal. An asynchronous time delay (t(s)) is introduced to produce the pulse-width modulated system output signal (y(s)). The circuitry performs digital to analog conversion (DAC) to the pulse-width modulated system output signal to produce a DAC output signal (490, 490). The DAC output signal or its summation with the passband signal component is integrated to produce the feedback signal component. Additional, multiple-order embodiments include sequential feedback paths or carrier-shaping functions.

A continuous-time sigma-delta modulator includes a VCO-based quantizer, a rotator, a truncation circuit and a digital-to-analog converter (DAC). The VCO-based quantizer is arranged to generate a thermometer code based on an input signal and a feedback signal. The rotator is coupled to the VCO-based quantizer, and is arranged to generate a phase-shifted thermometer code based on the thermometer code and a phase shift, and generate a rearranged thermometer code based on the phase-shifted thermometer code to comply with a specific pattern. The truncation circuit is coupled to the rotator, and is arranged to extract a most significant bit (MSB) part from the rearranged thermometer code. The DAC is coupled to the truncation circuit, and is arranged to generate the feedback signal according to at least the MSB part. Two alternative continuous-time sigma-delta modulators are also disclosed.

A delta sigma modulator which has improved the dynamic range. The modulator has a plurality of ADCs and a plurality of DACs, the plurality of ADCs and DACs are connected in a loop. The plurality of ADCs are coupled with an incoming analog signal. A clock generator provides a plurality of clock signals which control the plurality of ADCs and the plurality of DACs, the clock signals being offset relative to each other in the time domain thereby enabling each ADC in the plurality of ADCs one at a time and each DAC in the plurality of DACs one at a time so that the modulator processes data in the incoming analog signal in an interleaved fashion. The delta sigma modulator has an Nth order filter in a forward path of the loop.

System and methods for input path matching in pipelined continuous-time Analog-to Digital Converters (ADCs), including pipelined Continuous-Time Delta Sigma Modulator (CTDSM) based ADCs, includes an input delay circuit disposed in a continuous-time input path from an input of an analog input signal to a first summing circuit of the continuous-time ADC. At least one digital delay line is disposed between an output of an earlier stage sub-ADC (of a plurality of pipelined sub-ADCs) and a sub-digital-to-analog converter (DAC) that is coupled to the first summing circuit, and between the earlier stage sub-ADC and a digital noise cancellation filter. The digital delay line(s) is configured to enable calibration of delay of output of the earlier stage sub-ADC provided to the sub-DAC and the digital noise cancellation filter in accordance with process variations of the input delay match circuit to minimize residue output at first summing circuit.

A CT-SDADC of the present disclosure converts the analog input signal from a representation in an analog signal domain to a representation in a digital signal domain to provide the digital output signal. The CT-SDADC achieves the analog-to-digital conversion and ELDC by switching between two phases in the SAR sub-ADC: a sampling phase and a conversion phase. During the sampling phase, the SAR sub-ADC captures the analog input signal across multiple arrays of switchable capacitors. The conversion phase comprises a number of steps, and one or more bits of the digital output signal are resolved at each step of the conversion phase. A portion of the SC-DAC is driven by the delayed CT-SDADC output during the conversion phase to effectively compensate for excess loop delay caused by the CT-SDADC feedback loop.

A delta-sigma modulator includes a signal subtraction circuit, a loop filter, a quantizer, a digital-to-analog converter (DAC), and a control circuit. The signal subtraction circuit subtracts an analog feedback signal from an analog input signal to generate a difference signal. The loop filter performs a filtering operation upon the difference signal to generate a filtered signal. The quantizer quantizes the filtered signal into a digital out put signal, wherein at least one inherent circuit characteristic of the quantizer are adjusted in response to a digital code input. The DAC generates the analog feedback signal according to the digital output signal. The control circuit generates the digital code input to the quantizer for setting an excess loop delay (ELD) compensation.

A continuous time delta sigma modulator includes a summing circuit, a loop filter, an extraction circuit, a quantizer and a digital to analog converter. The summing circuit is arranged for subtracting a feedback signal by an input signal to generate a residual signal. The loop filter includes a plurality of amplifying stages connected in series and is arranged to receive the residual signal to generate a filtered residual signal. The extraction circuit is arranged for extracting a current from one of the amplifying stages and forwarding the extracted current to a following one of the amplifying stages. The quantizer is arranged for generating a digital output signal according to the filtered residual signal. The digital to analog converter is arranged for performing a digital to analog converting operation upon a signal derived from the digital output signal to generate the feedback signal to the summing circuit.