A signal processing circuit is provided. The signal processing circuit includes an analog-front-end circuit and a filter circuit. The analog-front-end circuit is configured to receive a sensing signal from a touch panel and perform a signal capture operation on the sensing signal to output a current signal. The filter circuit is coupled to the analog-front-end circuit. The filter circuit is configured to receive the current signal from the analog-front-end circuit and perform a signal filter operation on the current signal to output a first voltage signal. The filter circuit includes an anti-aliasing filter and a comb filter coupled in series.

A method and apparatus for utilizing a wideband radio frequency filter to capture an FM frequency band and configuring the characteristics of a delta-sigma modulator in order to processes desired signals within the FM frequency band. Specifically, the system and method are operative to receive a plurality of FM signals within an FM frequency band, filter the frequency band using a wideband filter, modulating the plurality of FM signals using a delta sigma modulator, down converting and processing the desired signals in parallel.

A Sigma-Delta () modulator for converting an analog input signal having a frequency bandwidth around a variable center frequency f.sub.0 to a digital output signal at a sampling frequency f.sub.s. The modulator comprises a quantizer (420) for generating the digital output signal and a loop filter for shaping the quantization noise. The loop filter comprises at least one subfilter (430, 410) centered around a frequency f.sub.0 and constant noise shaping coefficients (451, 452, 453). The modulator further comprises a tunable delay element (455), a frequency adjuster (480) for adjusting the sampling frequency f.sub.s such that the normalized center frequency f.sub.0/f.sub.s is constant, and a delay adjuster (490) for adjusting the loop delay t.sub.d implemented by the quantizer and the tunable delay element (455), such that the normalized loop delay t.sub.d/T.sub.s falls in a predetermined range [t.sub.min, t.sub.max], where T.sub.s=1/f.sub.s.

A continuous-time analog-to-digital converter (ADC) includes a plurality of integrators selectively coupled in series. The ADC may further include a quantizer with excess loop delay (ELD) compensation. The quantizer may be coupled in series to a least one integrator. The ELD compensation may be programmable based on a transfer function of the ADC. The ADC may further include parallel digital-to-analog converters (DACs). Each DAC may have an input coupled to an output of the quantizer, and an output coupled to an input of a corresponding integrator. The ADC may further include a bypass path coupled to an input or output of one of the integrators. The bypass path may be configured to selectively bypass one or more of the integrators to change the transfer function of the ADC.

Certain aspects of the present disclosure provide methods and apparatus for implementing sampling rate scaling of an excess loop delay (ELD)-compensated continuous-time delta-sigma modulator (CTDSM) analog-to-digital converter (ADC). One example ADC generally includes a loop filter; a quantizer having an input coupled to an output of the loop filter; one or more digital-to-analog converters (DACs), each having an input coupled to an output of the quantizer, an output coupled to an input of the loop filter, and a data latch comprising a clock input for the DAC coupled to a clock input for the ADC; and a clock delay circuit having an input coupled to the clock input for the ADC and an output coupled to a clock input for the quantizer.

A delta-sigma modulator (DSM) includes: a first summation circuit coupled to an input signal for subtracting an error feedback signal from the input signal; a tunable signal transfer function coupled to the first summation circuit for setting a desired pole in a frequency response of the DSM; a second summation circuit coupled to the tunable signal transfer function for adding a noise transfer function to an output of the tunable signal transfer function; and a quantizer coupled to the second summation circuit for quantizing an output of the second summation circuit to generate an output of the DSM. The output of the DSM is used as feedback to the first summation circuit as the error feedback signal, and the tunable signal transfer function is dynamically tuned to allow selecting and tuning a center frequency and a bandwidth of the DSM.

Certain aspects of the present disclosure provide methods and apparatus for implementing sampling rate scaling of an excess loop delay (ELD)-compensated continuous-time delta-sigma modulator (CTDSM) analog-to-digital converter (ADC). One example ADC generally includes a loop filter; a quantizer having an input coupled to an output of the loop filter; one or more digital-to-analog converters (DACs), each having an input coupled to an output of the quantizer, an output coupled to an input of the loop filter, and a data latch comprising a clock input for the DAC coupled to a clock input for the ADC; and a clock delay circuit having an input coupled to the clock input for the ADC and an output coupled to a clock input for the quantizer.

A wide bandwidth radio system designed to adapt to various global radio standards and, more particularly, to a radio receiver composed of a demodulator operative to work in a delta sigma mode and a Nyquist mode, and wherein a filter and feedback loop may utilized in response to the modulation mode of an RF signal.

A method and apparatus for adjusting a bandwidth of a sigma delta converter by adjusting a reference voltage provided to the sigma delta converter. The apparatus includes a switched capacitor digital-to-analog converter in the feedback loop of the sigma delta modulator. The sigma delta modulator determines the bandwidth mode of the converter and adjusts the reference voltage to deliver high performance functionality. In one embodiment, a multi-bit digital signal is received by the digital-to-analog converter. The reference voltage is provided to multiple capacitive circuits of the digital-to-analog converter and the capacitive circuits are activated and deactivated based on the multi-bit digital signal. The digital-to-analog converter, thus, provides a feedback analog signal using dynamic element matching.

A touch control detection system, a delta-sigma modulator and a modulating method thereof are provided. The delta-sigma modulator includes a quantizer and N integrating units. The quantizer generates a modulating result signal. The integrating units are coupled in series. Each of the integrating receives an input signal, and each of the integrating units receives a plurality of gain parameters, N is a positive integer. The quantizer quantizes a signal on an output end of the N.sup.th stage integrating unit according to an error signal for generating the modulating result signal. A center frequency of a noise transfer function (NTF) of the delta-sigma modulator is adjusted according to the gain parameters, and the gain parameters are determined according to a frequency of the input signal.