A noise-shaping enhanced (NSE) gated ring oscillator (GRO)-based ADC includes a delay which delays and feedbacks an error signal to an input of the NSE GRO-based ADC. The feedback error signal provides an order of noise-shaping and the error signal is generated at the input of the NSE GRO-based ADC from an input signal, the feedback error signal, and a front-end output. A voltage-to-time converter converts the error signal to the time domain. A GRO outputs phase signals from the time domain error signal by oscillating when the error signal is high and inhibiting oscillation otherwise. A quantization device quantizes the phase signals to generate the front-end output. A quantization extraction device determines a quantization error from the quantized phase signals. A time-to-digital converter digitizes the quantization error to generate a back-end output. An output device generates a second order noise-shaped output based on the front-end and the back-end outputs.

In described examples, a phase locked loop (PLL) has a first phase detector cell (PD) that has a gain polarity. The first PD cell has a phase error output and inputs coupled to a reference frequency signal and a feedback signal. A second PD cell has an opposite gain polarity. The second PD cell has a phase error output and inputs coupled to the reference frequency signal and the feedback signal. A loop filter has a feedforward path and a (lossy) integrating path coupled to an output of the filter. The feedforward path has a third PD cell that has phase error output AC-coupled to the filter output. The integrating path includes an opamp that has an inverting input coupled to the first PD cell phase error output and a non-inverting input coupled to the second PD cell phase error output.

A signal processing system may include a sensor readout channel configured to convert an electronic signal into a digital quantity. The sensor readout channel may include a first-order sigma-delta modulator having a modulator input and a modulator output, first outside chopping switches located at the modulator input, second outside chopping switches located at the modulator output, an auxiliary path having an analog-to-digital converter (ADC) having an auxiliary path input and an auxiliary path output, the auxiliary path input configured to receive as its input signal a signal output by a memory element of the first-order sigma-delta modulator, and a signal combiner configured to combine a modulator output signal generated by the first-order sigma-delta modulator with an auxiliary path output signal generated by the auxiliary path to generate a combined output signal.

A phase rotator control circuit is provided. The phase rotator control circuit is coupled to a phase rotator core and includes a first set of transistors coupled to receive digital control signals. The first set of transistors is coupled to a second set of transistors configured and arranged to form a filtered current mirror. An output of the filtered current mirror is coupled to provide an analog phase control signal to the phase rotator core.

An ANC system is provided, including an AD converter performing an AD conversion on an external noise signal; an ANC signal generator generating an ANC signal for canceling a noise component arriving at ears of a user based on an output signal of the AD converter; a level detector detecting a level of the output signal and causes the ANC signal generator to power down in response to the level; and a zero-cross detector detecting a zero-cross timing of the ANC signal. The level detector starts measuring a time when the level is equal to or less than a first threshold value, and causes the ANC signal generator to perform a power down operation when the zero-cross timing is detected after the measured time exceeds the predetermined value, and causes the ANC signal generator to exit from the power down operation when the level exceeds a second threshold value.

An ANC system is provided, including an AD converter performing an AD conversion on an external noise signal; an ANC signal generator generating an ANC signal for canceling a noise component arriving at ears of a user based on an output signal of the AD converter; a level detector detecting a level of the output signal and causes the ANC signal generator to power down in response to the level; and a zero-cross detector detecting a zero-cross timing of the ANC signal. The level detector starts measuring a time when the level is equal to or less than a first threshold value, and causes the ANC signal generator to perform a power down operation when the zero-cross timing is detected after the measured time exceeds the predetermined value, and causes the ANC signal generator to exit from the power down operation when the level exceeds a second threshold value.

A MASH type sigma delta AD converter includes a modulator, an analog filter filtering an extraction signal obtained by extracting a probe signal and an quantization error generated in a quantizer within a sigma delta modulator, a low speed AD converter performing an AD conversion of an output signal of the analog filter, a first adaptive filter searching for a transfer function of the sigma delta modulator, a second adaptive filter searching for a transfer function from an output of the modulator to the low speed AD converter via the analog filter, and a noise cancellation circuit cancelling the probe signal and the quantization error included in an output signal of the quantizer using the search results by the first and second adaptive filters.

In described examples, a phase locked loop (PLL) has a first phase detector cell (PD) that has a gain polarity. The first PD cell has a phase error output and inputs coupled to a reference frequency signal and a feedback signal. A second PD cell has an opposite gain polarity. The second PD cell has a phase error output and inputs coupled to the reference frequency signal and the feedback signal. A loop filter has a feedforward path and a (lossy) integrating path coupled to an output of the filter. The feedforward path has a third PD cell that has phase error output AC-coupled to the filter output. The integrating path includes an opamp that has an inverting input coupled to the first PD cell phase error output and a non-inverting input coupled to the second PD cell phase error output.

In described examples, a feedback loop has phase detection (PD) circuitry that has a reference input to receive a reference frequency signal, a feedback input to receive a feedback signal, and phase difference outputs. A phase to digital converter (P2DC) includes a first phase to charge converter (PCC) that has a gain polarity and a first phase error output; a second PCC that has an opposite gain polarity and a second phase error output. A differential loop filter has an amplifier with an inverting input coupled to the first phase error output and a non-inverting input coupled to the second phase error output. An analog to digital converter (ADC) has an input coupled to an output of the differential loop filter. A feedback path is coupled to the output of the P2DC, with an output of the feedback path providing the feedback signal to the PD feedback input.

A signal processing system may include a sensor readout channel configured to convert an electronic signal into a digital quantity. The sensor readout channel may include a first-order sigma-delta modulator having a modulator input and a modulator output, first outside chopping switches located at the modulator input, second outside chopping switches located at the modulator output, an auxiliary path comprising an analog-to-digital converter (ADC) having an auxiliary path input and an auxiliary path output, the auxiliary path input configured to receive as its input signal a signal output by a memory element of the first-order sigma-delta modulator, and a signal combiner configured to combine a modulator output signal generated by the first-order sigma-delta modulator with an auxiliary path output signal generated by the auxiliary path to generate a combined output signal.