The present disclosure relates generally to the field of data encoding and decoding, and particularly to automorphism-based polar encoding and decoding apparatuses and methods, as well as computer program products embodying the method steps in the form of computer codes. More specifically, polar codes are designed such that their frozen bits support automorphisms described by a binary upper triangular matrix having a diagonal including at least one of zeros and units. Codewords generated using these polar codes may be subsequently subjected to automorphism-based polar decoding in an efficient manner and with a lower decoding latency compared to the conventional Successive Cancellation List decoding algorithms. Furthermore, the efficiency of the automorphism-based polar decoding may be increased even more if the automorphisms are based on matrix elements arranged above the diagonal in a vicinity of a bottom right corner of the binary upper triangular matrix.

Decoding sequentially received vector signaling codewords to obtain sequential sets of data bits, wherein elements of each vector signaling codeword are received in parallel over a plurality of wires, generating an incremental update of a plurality of error correction syndrome values based on each sequential set of data bits according to a check matrix, and upon decoding of a final vector signaling codeword, performing a final incremental update of the plurality of error correction syndrome values and responsively modifying data bits within the sequential sets of data bits by selecting a set of data bits from the sequential sets of data bits according to a symbol position index determined from the plurality of error correction syndrome values, the selected set of data bits altered according to a bit error mask determined from a first error correction syndrome value of the plurality of error correction syndrome values.

In one embodiment the method includes providing a bidirectionally linked blockchain structure; generating an additional block for expanding the blockchain structure, which includes the data to be stored and is intended to be linked bidirectionally to the last block of the blockchain structure, the last block of the blockchain structure including stored data; and calculating a first block-dependent linking function for bidirectionally linking the last block to the additional block. The calculation of the linking function including calculating a combined block-dependent check value of the last block and of the additional block, using the data stored in the last block and the data to be stored in the additional block; and associating the combined check value with a block-independent, linking process-specific function. The method further includes adding the first block-dependent linking function to the last block and to the additional block.

A method includes: sending a first boundary bit block; sequentially sending an Ith bit block; determining a first parity check result and a second parity check result, where a check object of the first parity check result includes m consecutive bits of each bit block in the N bit blocks, a check object of the second parity check result includes n consecutive bits of each bit block in the N bit blocks, and at least one of m and n is greater than or equal to 2; and sending a second boundary bit block, the first parity check result, and the second parity check result.

The disclosure proposes a technique for achieving validity decision performance of a suitable level in communication and broadcasting systems using a polar code. The polar code is a channel code in which it is difficult to use a syndrome check due to a successive cancellation (SC)-based decoding operation and coding structure. Accordingly, in the communication of the related art and broadcasting systems using the polar code, a validity check of a decoding result has been performed by using a path-metric (PM) generated during decoding and a concatenated error detection code, such as a cyclic redundancy check (CRC) code. However, it is difficult to achieve target error detection performance only via such methods when the length of the CRC code is short or when input and output lengths of a code are short. In this regard, an embodiment of the disclosure proposes a method for obtaining a Euclidean distance-based metric between a received signal and a decoded signal by using an estimated codeword output bit sequence, and performing post error detection based on this.

A communication apparatus for forward error correction and detection using polar codes comprising a polar encoder that encodes an input vector to output a codeword using a generator matrix of polar code wherein the input vector is a cyclic redundancy check (CRC) codeword of an information block; a memory that stores a frozen set including frozen bit indices and a non-frozen set including non-frozen bit indices sorted in order of error probabilities; and a controller that is configured to take as input the CRC codeword where CRC bits appended to the end of information block and interleave the CRC codeword using at least one of a first interleaver and second interleaver before feeding the CRC codeword to polar encoder such that the first interleaver places at least one CRC bit earlier than its original position in the CRC codeword and a second interleaver selects at least one bit from the CRC codeword whose corresponding index in a parity check matrix of the CRC code has the highest column weight and puts it in the non-frozen bit index with highest error probability.

Provided are a Cyclic Redundancy Check (CRC) circuit, and a method and an apparatus thereof, a chip and an electronic device, which belong to the technical field of computers. Herein, the cyclic redundancy check circuit may include: a configuration module configured to acquire configuration information and an information field, a CRC arbitration module configured to determine a generator polynomial according to the configuration information, a CRC control module configured to respond to triggering of the CRC arbitration module and output a clock signal, a coefficient corresponding to each power in the generator polynomial and the information field, a parallel iteration module configured to respond to the clock signal and implement parallel iteration for the information field according to the coefficient corresponding to the each power in the generator polynomial, as to output an iteration result, and a CRC output module configured to package the information field according to the iteration result.

Through the identification of different packet-types, packets can be handled based on an assigned packet handling identifier. This identifier can, for example, enable forwarding of latency-sensitive packets without delay and allow error-sensitive packets to be stored for possible retransmission. In another embodiment, and optionally in conjunction with retransmission protocols including a packet handling identifier, a memory used for retransmission of packets can be shared with other transceiver functionality such as, coding, decoding, interleaving, deinterleaving, error correction, and the like.

Through the identification of different packet-types, packets can be handled based on an assigned packet handling identifier. This identifier can, for example, enable forwarding of latency-sensitive packets without delay and allow error-sensitive packets to be stored for possible retransmission. In another embodiment, and optionally in conjunction with retransmission protocols including a packet handling identifier, a memory used for retransmission of packets can be shared with other transceiver functionality such as, coding, decoding, interleaving, deinterleaving, error correction, and the like.

The disclosure provides a method and a device in a User Equipment (UE) and a base station for wireless communication. A first node generates a first bit block, performs channel coding and then transmits a first radio signal. The first bit block comprising all bits in a second bit block and all bits in a third bit block is used for an input of the channel coding, and an output of the channel coding is used for generating the first radio signal. A Cyclic Redundancy Check (CRC) bit block of a fourth bit block is used for generating the third bit block. The fourth bit block comprises all bits in the second bit block and all bits in a fifth bit block, the bits in the fifth bit block are of fixed values, and the fifth bit block is composed of K bits, the K being a positive integer.