Patent classifications
H03M13/093
Robust visual light communication for vehicle-to-vehicle communication
Method and apparatus are disclosed for robust visual light communication for vehicle-to-vehicle communication. An example vehicle includes a visual light communication (VLC) transmitter, a VLC communication receiver, and a VLC module. The VLC module sends a first handshake message including characteristics of the VLC transmitter and the VLC receiver using a first level of error correction. The VLC module also adjusts transmission parameters based on a received second handshake message. Additionally, the VLC module transmits data using a second level of error correction.
Convolutional code decoder and convolutional code decoding method
The invention discloses a convolutional code decoder and a convolutional code decoding method. The convolutional code decoder performs decoding operation according to a received data and an auxiliary data to obtain a target data and includes an error detection data generation circuit, a channel coding circuit, a selection circuit, and a Viterbi decoding circuit. The error detection data generation circuit performs an error detection operation on the auxiliary data to obtain an error detection data. The channel coding circuit, coupled to the error detection data generation circuit, performs channel coding on the auxiliary data and the error detection data to obtain an intermediate data. The selection circuit, coupled to the channel coding circuit, generates a to-be-decoded data according to the received data and the intermediate data. The Viterbi decoding circuit, coupled to the selection circuit, decodes the to-be-decoded data to obtain the target data.
Hardware-based Dynamic Cyclic-Redundancy Check (CRC) Generator for Automotive Application
Embodiments include methods performed by a copy engine of a computing device for generating a cyclic redundancy check (CRC) in a safety network, including copying a first dataset received from an interface bus to obtain a first dataset copy, copying a second dataset received from the interface bus to obtain a second dataset copy, generating, via a first stream-wise CRC engine in the hardware of the copy engine, a first CRC value for the first dataset copy and, in parallel, generating, via a second stream-wise CRC engine in the hardware of the copy engine, a second CRC value for the second dataset copy, transmitting, to a processor of the computing device, a first stream-wise CRC message including the first dataset copy and the first CRC value, and a second stream-wise CRC message including the second dataset copy and the second CRC value.
Performing a cyclic redundancy checksum operation responsive to a user-level instruction
In one embodiment, the present invention includes a method for receiving incoming data in a processor and performing a checksum operation on the incoming data in the processor pursuant to a user-level instruction for the checksum operation. For example, a cyclic redundancy checksum may be computed in the processor itself responsive to the user-level instruction. Other embodiments are described and claimed.
Optical module, optical module system and monitor method using the same
The present invention relates to an optical module and optical module system using the same. The optical module comprises a transceiving unit, an antenna and an MCU. The transceiving unit receives control commands from one or more control computers via the antenna and transfers them to the MCU. Then the MCU processes the control commands and provides feedback information to the one or more control computers through the transceiving unit. In the optical module of the present invention, as a result of an additional IOT wireless unit, the optical module is capable of communicating with remote control computers, thereby achieving remote testing and control for optical modules, instead of using conventional control methods for optical modules.
Error detection or correction of a portion of a codeword in a memory device
Example embodiments described herein may relate error detection and correction on a portion of a codeword in a memory device.
DATA TRANSMISSION METHOD, SENDING DEVICE, AND RECEIVING DEVICE
A data transmission method, a sending device, and a receiving device are provided. A sending device obtains information data, encodes the information data by using a quasi-cyclic low-density parity-check (LDPC) code matrix, modulates the encoded data to obtain first data, and sends the first data. A receiving device obtains second data, demodulates the second data to obtain to-be-decoded data, and decodes the to-be-decoded data by using a block matrix in an LDPC code matrix, where the block matrix is a submatrix in the quasi-cyclic LDPC matrix, and in the quasi-cyclic LDPC matrix, a row weight of a row (H1) is greater than or equal to a row weight of a row H, or a row weight of a row (H1) is less than or equal to a row weight of a row H. In this way, decoding efficiency can be improved.
DEVICE AND METHOD FOR MONITORING A DIGITAL CONTROL UNIT WITH REGARD TO FUNCTIONAL SAFETY, AND CONTROLLER
A device for monitoring a digital control unit with regard to functional safety is proposed. The device comprises an interface configured to receive a control signal of the digital control unit for a circuit component. The control signal represents a digital value. Furthermore, the device comprises a timer circuit configured to output an associated timer value in each case for successive points in time. The device furthermore comprises a hash value generator, which is configurable, in response to a change in the digital value, to recalculate a hash value on the basis of the change in the digital value and the timer value at the point in time of the change in the digital value.
Performing a cyclic redundancy checksum operation responsive to a user-level instruction
In one embodiment, the present invention includes a method for receiving incoming data in a processor and performing a checksum operation on the incoming data in the processor pursuant to a user-level instruction for the checksum operation. For example, a cyclic redundancy checksum may be computed in the processor itself responsive to the user-level instruction. Other embodiments are described and claimed.
Fast update of data packet checksums
A device includes a processor and a checksum module, wherein the checksum module calculates, for first data, an updated checksum that complies with Internet Engineering Task Force Request For Comments Number 1624 using twos-complement arithmetic. The processor replaces the original checksum with the updated checksum to update a data packet.