Methods, systems, and devices related to mapping a plurality of pairs of bits of a memory transfer block (MTB) to a plurality of linked (LK) die input/output (LDIO) lines coupling a LK die to an interface (IF) die. The plurality of pairs of bits of the MTB can be communicated from the LK die to the IF die via the plurality of LDIO lines. Responsive to a failure of one of the plurality of LDIO lines, a Bose-Chaudhuri-Hocquenghem (BCH) error correction can be performed on the pairs of bits mapped to the failed LDIO line. Each of the plurality of pairs of bits is a respective symbol for the BCH error correction.

Examples pertaining to bit selection for polar coding incremental-redundancy hybrid automatic repeat request (IR-HARQ) are described. An apparatus (e.g., UE) generates a re-transmission polar code block (CB) in a polar incremental redundancy HARQ (IR-HARQ) procedure. The apparatus then transmits the re-transmission polar CB as a re-transmission of an initial transmission of an initial polar code carrying a plurality of information bits. In generating the re-transmission polar CB, the apparatus selects one or more re-transmission information bits from the plurality of information bits.

A collector (110) included in a data collection apparatus (100) performs data collection to collect data from a PLC (604, 605). A controller (150) included in the data collection apparatus (100) determines whether the collector (110) is valid depending on whether the collector (110) at a time when an instruction to start the data collection is provided matches the collector (110) at a preset time, and causes the collector (110) to start the data collection in response to the collector (110) being valid.

Polar Codes for Downlink Control Channels for Wireless Networks A technique is provided for decoding downlink control information that was encoded using polar encoding, the technique including: attempting, based on an initial assumption by a user device of a segmented downlink control information, to decode a first codeword provided via a user device-specific resource, the first codeword including a first downlink control information segment and a pointer to a second downlink control information segment of a segmented downlink control information; decoding, if the attempting to decode is successful, based on the pointer, a second codeword that includes the second downlink control information segment of the segmented downlink control information; and otherwise, if the attempting to decode is unsuccessful, making an assumption of a non-segmented downlink control information and decoding a third codeword to obtain a non-segmented downlink control information.

Single error correction (“SEC”) code and triple error detection (“TED”) code are used to optimize bandwidth and resilience under multiple bit failures. One or more errors in data stored in duplicated registers are detected and corrected using the SEC code and TED code where simultaneous read operations are produced with two copies of data for each of the duplicated registers for a multi-port banked memory array. The SEC code and TED code may be included in each of the two data copies of the simultaneous read operations.

Various embodiments are provided for enhanced error correction using single error correction (SEC) code and triple error detection (TED) code to optimize bandwidth and resilience under multiple bit failures by a processor. One or more errors may be detected and corrected in duplicated registers using an SEC code and TED code where simultaneous read operations are produced with two copies of data for each of the duplicated registers for a multi-port banked memory array. The SEC code and TED code may be included in each of the two data copies of the simultaneous read operations.

An embodiment method includes receiving, by a first user equipment (UE), a message, for a second UE, transmitted over a plurality of resource blocks (RBs) on behalf of a communications controller and determining a plurality of log-likelihood ratios (LLRs) in accordance with the received plurality of RBs. The method also includes transmitting, a subset of the determined LLRs to the second UE.

According to one general aspect, an apparatus may include a storage element configured to store both data and metadata, wherein each piece of data is associated with and stored with a corresponding piece of metadata. The apparatus may include a controller processor. The controller processor may be configured to, in response to a piece of data being written to the apparatus: generate a piece of metadata that includes a set of parameters to facilitate a at least partial repair of a block information map, and embed the piece of metadata with the corresponding piece of data.

An error check and scrub (ECS) mode enables a memory device to perform error checking and correction (ECC) and count errors. An associated memory controller triggers the ECS mode with a trigger sent to the memory device. The memory device includes multiple addressable memory locations, which can be organized in segments such as wordlines. The memory locations store data and have associated ECC information. In the ECS mode, the memory device reads one or more memory locations and performs ECC for the one or more memory locations based on the ECC information. The memory device counts error information including a segment count indicating a number of segments having at least a threshold number of errors, and a maximum count indicating a maximum number of errors in any segment.

A method is disclosed comprising encoding a message into blocks, determining a collection of DNA symbols for each of the blocks from the encoded message, performing a second encoding of the determined collection of DNA symbols from the encoded message, detecting a presence of errors in the second encoding and establishing an authentication of each block and further using zero-knowledge protocol to securely authenticate the message without disclosing the actual message.