A method for checking a signal transmission of a specified message with a number of d bits from a sender to a receiver by a control unit using a linear block code generated via a coding tool, a channel model, and a specified linear feedback shift register, which is parameterized via a generator polynomial, wherein the residual error probability of different Markov-modulated Bernoulli processes is calculated, where boundary conditions for signal transmission can be specified by using a characterizing Markov-modulated Bernoulli process and also a linear feedback shift register, where integration of the calculation of the residual error probability is performed in a dynamic, intelligent control circuit such that the respective residual error probabilities can be determined for different generator polynomials.

A memory system includes; a memory device, a memory controller including a first interface, a second interface, and a first data processor having a first error correction code (ECC) engine, and a field programmable gate array (FPGA) including a third interface connected to the first interface, a fourth interface connected to the second interface, a fifth interface connected to an external host, and a second data processor having a second ECC engine. The memory controller may configure a normal write operation path or highly reliable write operation path.

In a method for computer-assisted operation of a memory unit, encoded data is saved in the memory unit. The data is retrieved and decoded after retrieval. The memory unit is monitored for errors in that a temporal sequence of computer-assisted checking operations is carried out for the memory unit. For first-time encoding of the data, each required application data set is generated or selected, containing check data segments. For each application data set, the check data segment is occupied by count data, which characterizes the checking operation being implemented. After retrieving and decoding the application data sets, an error is determined when the count data characterizes neither the checking operation being implemented nor the most recent completely implemented checking operation. The check data segment of the relevant application data set is occupied by count data, which characterizes the checking operation being implemented, if no error was determined.

Various aspects of the disclosure relate to encoding information and decoding information. In some aspects, the disclosure relates to an encoder and a decoder for Polar codes with HARQ. If a first transmission of the encoder fails, information bits associated with a lower quality channel may be retransmitted. At the decoder, the resulting decoded retransmitted bits may be used to decode the first transmission by substituting the retransmitted bits for the original corresponding (low quality channel) bits. In some aspects, to decode the first transmission, soft-combining is applied to the decoded retransmitted bits and the original corresponding (low quality channel) bits. In some aspects, CRC bits for a first transmission may be split between a first subset of bits and a second subset of bits. In this case, the second subset of bits and the associated CRC bits may be used for a second transmission (e.g., a retransmission).

Methods, systems, and devices for error protection for managed memory devices are described. In some examples, a memory system may receive data units from a host device. The data units may include respective sets of parity bits, and the memory system may perform an error detection operation on the data units. A first controller of the memory system may generate a protocol unit using data (e.g., a subset of data) from the data units. The protocol unit may include a set of parity bits (e.g., a different set of parity bits), and a second controller of the memory system may perform an error detection operation on the protocol unit. The second controller of the memory system may generate a data storage unit using data (e.g., a subset of data) from the protocol unit, and may store the data unit and another set of parity bits to a memory device.

Polar Codes for Downlink Control Channels for Wireless Networks A technique is provided for decoding downlink control information that was encoded using polar encoding, the technique including: attempting, based on an initial assumption by a user device of a segmented downlink control information, to decode a first codeword provided via a user device-specific resource, the first codeword including a first downlink control information segment and a pointer to a second downlink control information segment of a segmented downlink control information; decoding, if the attempting to decode is successful, based on the pointer, a second codeword that includes the second downlink control information segment of the segmented downlink control information; and otherwise, if the attempting to decode is unsuccessful, making an assumption of a non-segmented downlink control information and decoding a third codeword to obtain a non-segmented downlink control information.

A device for monitoring a digital control unit with regard to functional safety is proposed. The device comprises an interface configured to receive a control signal of the digital control unit for a circuit component. The control signal represents a digital value. Furthermore, the device comprises a timer circuit configured to output an associated timer value in each case for successive points in time. The device furthermore comprises a hash value generator, which is configurable, in response to a change in the digital value, to recalculate a hash value on the basis of the change in the digital value and the timer value at the point in time of the change in the digital value.

Methods, systems, and devices for error protection for managed memory devices are described. In some examples, a memory system may receive data units from a host device. The data units may include respective sets of parity bits, and the memory system may perform an error detection operation on the data units. A first controller of the memory system may generate a protocol unit using data (e.g., a subset of data) from the data units. The protocol unit may include a set of parity bits (e.g., a different set of parity bits), and a second controller of the memory system may perform an error detection operation on the protocol unit. The second controller of the memory system may generate a data storage unit using data (e.g., a subset of data) from the protocol unit, and may store the data unit and another set of parity bits to a memory device.

A semiconductor device includes a bitwise operation unit and a storage control unit. The bitwise operation unit performs a bitwise operation on first n-bit (n is an integer) data that is storage object data and second data of an n-bit bit pattern and generates third data of a bit pattern that the number of 1s and the number of 0s are almost the same as each other. The storage control unit stores the third data into a first storage destination of a storage unit and stores fourth data that is the third data or data that is converted into the third data by performing a bitwise operation that has been predetermined in advance on the data into a second storage destination of the storage unit.

A method is disclosed comprising encoding a message into blocks, determining a collection of DNA symbols for each of the blocks from the encoded message, performing a second encoding of the determined collection of DNA symbols from the encoded message, detecting a presence of errors in the second encoding and establishing an authentication of each block and further using zero-knowledge protocol to securely authenticate the message without disclosing the actual message.