An error check and scrub (ECS) mode enables a memory device to perform error checking and correction (ECC) and count errors. An associated memory controller triggers the ECS mode with a trigger sent to the memory device. The memory device includes multiple addressable memory locations, which can be organized in segments such as wordlines. The memory locations store data and have associated ECC information. In the ECS mode, the memory device reads one or more memory locations and performs ECC for the one or more memory locations based on the ECC information. The memory device counts error information including a segment count indicating a number of segments having at least a threshold number of errors, and a maximum count indicating a maximum number of errors in any segment.

In a system where a memory device performs on-die ECC, the ECC operates on N-bit data words as two (N/2)-bit segments, with a code matrix having a corresponding N codes that can be operated on as a first portion of (N/2) codes and a second portion of (N/2) codes to compute first and second error checks for first and second (N/2)-bit segments of the data word, respectively. In the code matrix, a bitwise XOR of any two codes in the first portion of the code matrix or any two codes in the second portion of the code matrix results in a code that is either not in the code matrix or is in the other portion of the code matrix. Thus, a miscorrected double bit error in one portion causes a bit to be toggled in the other portion instead of creating a triple bit error.

A parity check circuit may include a first signal combination unit for generating first to N.sup.th combination signals by combining first to N.sup.th signals, wherein a K.sup.th (K is a natural number of 2KN) combination signal of the first to N.sup.th combination signals is obtained by combining the first to K.sup.th signals of the first to N.sup.th signals, a parity check unit for detecting whether an error is present in the first to N.sup.th signals in response to the N.sup.th combination signal, a second signal combination unit for generating first to N.sup.th reconstruction signals by combining the first to N.sup.th combination signals, wherein a K.sup.th reconstruction signal of the first to N.sup.th reconstruction signals is obtained by combining a (K1).sup.th combination signal and the K.sup.th combination signal of the first to N.sup.th combination signals, and a signal storage unit for storing the first to N.sup.th reconstruction signals.

Provided is an information reconciliation method in a quantum key distribution system between a transmitter and a receiver, which includes receiving a parity bit from the transmitter through a quantum channel, correcting an error of a receiver quantum key by using the received parity bit, and removing a residual error of the receiver quantum key through an open channel by using a cascade protocol to harmonize the receiver quantum key with a transmitter quantum key, wherein the parity bit is generated at the transmitter by using turbo codes. This method may enhance quantum key generation efficiency.

A system and related method, including memory and processing circuitry, which is to receive data and corresponding expected error-detecting code value. The processing circuitry processes the data in at least two portions by calculating and storing, in memory, an error-detecting code value for the respective portion. The processing circuitry is then to calculate an overall error-detecting code value based on the respective error-detecting code values for the at least two portions. When the overall error-detecting code value does not match the expected error-detecting code value the processing circuitry is to correct at least one portion and process the corrected portions by calculating an updated error-detecting code value for a respective one of the corrected portions and calculating an updated overall error-detecting code value based on the updated error-detecting code value for each corrected portions and the stored error-detecting code values.

A memory control component encodes over-capacity data into an error correction code generated for and stored in association with an application data block, inferentially recovering the over-capacity data during application data block read-back by comparing error syndromes generated in detection/correction operations for respective combinations of each possible value of the over-capacity data and the read-back application data block.

A system and related method, including memory and processing circuitry, which is to receive data and corresponding expected error-detecting code value. The processing circuitry processes the data in at least two portions by calculating and storing, in memory, an error-detecting code value for the respective portion. The processing circuitry is then to calculate an overall error-detecting code value based on the respective error-detecting code values for the at least two portions. When the overall error-detecting code value does not match the expected error-detecting code value the processing circuitry is to correct at least one portion and process the corrected portions by calculating an updated error-detecting code value for a respective one of the corrected portions and calculating an updated overall error-detecting code value based on the updated error-detecting code value for each corrected portions and the stored error-detecting code values.

Various aspects of the disclosure relate to encoding information and decoding information. In some aspects, the disclosure relates to an encoder and a decoder for Polar codes with HARQ. If a first transmission of the encoder fails, information bits associated with a lower quality channel may be retransmitted. At the decoder, the resulting decoded retransmitted bits may be used to decode the first transmission by substituting the retransmitted bits for the original corresponding (low quality channel) bits. In some aspects, to decode the first transmission, soft-combining is applied to the decoded retransmitted bits and the original corresponding (low quality channel) bits. In some aspects, CRC bits for a first transmission may be split between a first subset of bits and a second subset of bits. In this case, the second subset of bits and the associated CRC bits may be used for a second transmission (e.g., a retransmission).

Methods, systems, and devices for error protection for managed memory devices are described. In some examples, a memory system may receive data units from a host device. The data units may include respective sets of parity bits, and the memory system may perform an error detection operation on the data units. A first controller of the memory system may generate a protocol unit using data (e.g., a subset of data) from the data units. The protocol unit may include a set of parity bits (e.g., a different set of parity bits), and a second controller of the memory system may perform an error detection operation on the protocol unit. The second controller of the memory system may generate a data storage unit using data (e.g., a subset of data) from the protocol unit, and may store the data unit and another set of parity bits to a memory device.