A system for software error-correcting code (ECC) protection or compression of original data using ECC data in a first memory is provided. The system includes a processing core for executing computer instructions and accessing data from a main memory, and a non-volatile storage medium for storing the computer instructions. The software ECC protection or compression includes: a data matrix for holding the original data in the first memory; a check matrix for holding the ECC data in the first memory; an encoding matrix for holding first factors in the main memory, the first factors being for encoding the original data into the ECC data; and a thread for executing on the processing core. The thread includes a Galois Field multiplier for multiplying entries of the data matrix by an entry of the encoding matrix, and a sequencer for ordering operations using the Galois Field multiplier to generate the ECC data.

Cable systems and assemblies integrate a reduced number of twin axial copper pairs to transmit and received in a full-duplex transmission signals at transmission speeds greater than or equal to one hundred Giga bytes per second. The reduced number of twin axial copper pairs comprise four or less twin axial copper pairs, in which each pair forms a single twin axial full-duplex cable for passive or active communication of the signals. A processor can be integrated with the twin axial copper pairs operate to encode the signals for fast transmission speeds.

A transceiver architecture can contain an encoder and a decoder for communicating high speed transmissions. The encoder can modulate signal data based on a product code of an E8 lattice based on binary and non binary codes that creates an extended Hamming code of a multi-level structure of E8 with four bit estimates. During decoding the multi-level E8 decoding is performed on the Hamming code and then row decoding and column decoding are performed. Then lattice decoding is performed on the output of the row and column decoding. This decoding process can be iteratively performed a predetermined number of times until the encoded bits are decoded.

This invention discloses a method and system for generating a private key and a corresponding public key. These keys can be used for encrypting a message into a ciphertext for transmission through an insecure communication channel, and for decrypting said ciphertext into a clear plaintext. The goal of the present invention is to provide encryption and decryption methods of the McEliece type which are capable of improving the security level of a post-quantum cryptosystem. In one embodiment, this object is achieved by three methods: a method for creating a public key from a private linear code generator matrix, a method for encrypting a message into a ciphertext and a method for decrypting the ciphertext into a plaintext. The key generation and encryption methods of the present invention comprises the following steps: selecting an [n, k] linear code generator matrix G.sub.s=[g.sub.0, . . . , g.sub.n] over GF(q) as the private key, where k, r, n and q are positive integers and where g.sub.0, . . . , g.sub.n1 are length k column vectors; selecting kr random matrices C.sub.0, . . . , C.sub.n1; selecting a kk non-singular matrix S; selecting an n(r+1)n(r+1) matrix A; selecting an n(r+1)n(r+1) permutation matrix P; and setting the public key as G=S[g.sub.0, C.sub.0, . . . , g.sub.n1, C.sub.n1]AP. receiving a public key G, which is a kn(r+1) matrix over a finite field GF(q); generating an error vector e having elements in GF(q) and having a predetermined weight t; and encrypting a message vector m to a ciphertext vector y=mG+e.
The main difference between the proposed cryptosystem and known variants of the McEliece cryptosystem consists in the way the private generator matrix is disguised into the public one by inserting and mixing random columns within the private generator matrix.

An accelerated erasure coding system includes a processing core for executing computer instructions and accessing data from a main memory, and a non-volatile storage medium for storing the computer instructions. The processing core, storage medium, and computer instructions are configured to implement an erasure coding system, which includes: a data matrix for holding original data in the main memory; a check matrix for holding check data in the main memory; an encoding matrix for holding first factors in the main memory, the first factors being for encoding the original data into the check data; and a thread for executing on the processing core. The thread includes: a parallel multiplier for concurrently multiplying multiple entries of the data matrix by a single entry of the encoding matrix; and a first sequencer for ordering operations through the data matrix and the encoding matrix using the parallel multiplier to generate the check data.

A method and an apparatus for encoding and decoding in an electronic device are provided. In a decoding method, at least one parity symbol is received. A Cauchy matrix is generated using the at least one parity symbol. A Cauchy submatrix is configured from the Cauchy matrix based on the number of at least one lost data symbol and an inverse matrix of the Cauchy submatrix is calculated. At least one parity symbol corresponding to the at least one lost data symbol is updated. The at least one lost data symbol is recovered using the updated at least one parity symbol.

A system for software error-correcting code (ECC) protection or compression of original data using ECC data in a first memory is provided. The system includes a processing core for executing computer instructions and accessing data from a main memory, and a non-volatile storage medium for storing the computer instructions. The software ECC protection or compression includes: a data matrix for holding the original data in the first memory; a check matrix for holding the ECC data in the first memory; an encoding matrix for holding first factors in the main memory, the first factors being for encoding the original data into the ECC data; and a thread for executing on the processing core. The thread includes a Galois Field multiplier for multiplying entries of the data matrix by an entry of the encoding matrix, and a sequencer for ordering operations using the Galois Field multiplier to generate the ECC data.

This application relates to the field of wireless communications technologies, and discloses an encoding method and apparatus, to improve accuracy of reliability calculation and ordering for polarized channels. The method includes: obtaining a first sequence used to encode K to-be-encoded bits, where the first sequence includes sequence numbers of N polarized channels, the first sequence is same as a second sequence or a subset of the second sequence, the second sequence comprises sequence numbers of N.sub.max polarized channels, and the second sequence is the sequence shown in Sequence Q11 or Table Q11, K is a positive integer, N is a positive integer power of 2, n is equal to or greater than 5, KN, N.sub.max=1024; selecting sequence numbers of K polarized channels from the first sequence; and performing polar code encoding on K the to-be-encoded bits based on the selected sequence numbers of the K polarized channels.

An accelerated erasure coding system includes a processing core for executing computer instructions and accessing data from a main memory, and a non-volatile storage medium for storing the computer instructions. The processing core, storage medium, and computer instructions are configured to implement an erasure coding system, which includes: a data matrix for holding original data in the main memory; a check matrix for holding check data in the main memory; an encoding matrix for holding first factors in the main memory, the first factors being for encoding the original data into the check data; and a thread for executing on the processing core. The thread includes: a parallel multiplier for concurrently multiplying multiple entries of the data matrix by a single entry of the encoding matrix; and a first sequencer for ordering operations through the data matrix and the encoding matrix using the parallel multiplier to generate the check data.

A method includes receiving a bit string at a processor, performing an error correction, and causing transmission of a modulated signal. The error correction includes identifying a set of binary strings based on the bit string, mapping each binary string from the set of binary strings to a first abelian group element from a set of first abelian group elements, and applying a generalization of polar codes to the set of first abelian group elements to produce a set of second abelian group elements. The error correction also includes mapping each of the second abelian group elements to an in-phase/quadrature (I/Q) point from a set of I/Q points and identifying real-valued points based on the set of I/Q points, each of the real-valued points representing an I/Q point from the set of I/Q points. The modulated signal has a modulation that is based on the real-valued points.