In an embodiment, a processor includes error correction code (ECC) circuitry to: receive a codeword comprising data bits and parity bits; generate, using a parity checking matrix H, a syndrome vector associated with the received codeword, where the parity-checking matrix H comprises a data segment comprising N data columns and a parity segment comprising K parity columns, where a total quantity of data columns in the data segment with even weight is equal to N+K2.sup.(K1)+1; and detect an adjacent two bit error in the codeword based on a comparison of the syndrome vector to the parity checking matrix H. Other embodiments are described and claimed.

An embodiment method includes: performing balancing processing on a data stream that includes a plurality of sub-data stream segments, and performing segment de-interleaving on a data stream obtained after the balancing processing. The method further includes separately performing forward error correction (FEC) decoding on each sub-data stream segment in a data stream obtained after the segment de-interleaving. The method further includes performing, according to a balancing termination state of each sub-data stream segment obtained after previous balancing processing, balancing processing on each sub-data stream segment obtained after the FEC decoding, and performing FEC decoding on the data stream obtained after balancing processing is performed on each sub-data stream segment. When it is determined that a preset iteration termination condition is met, the method includes outputting the data stream obtained after the FEC decoding.

An embodiment method includes: performing balancing processing on a data stream that includes a plurality of sub-data stream segments, and performing segment de-interleaving on a data stream obtained after the balancing processing. The method further includes separately performing forward error correction (FEC) decoding on each sub-data stream segment in a data stream obtained after the segment de-interleaving. The method further includes performing, according to a balancing termination state of each sub-data stream segment obtained after previous balancing processing, balancing processing on each sub-data stream segment obtained after the FEC decoding, and performing FEC decoding on the data stream obtained after balancing processing is performed on each sub-data stream segment. When it is determined that a preset iteration termination condition is met, the method includes outputting the data stream obtained after the FEC decoding.

A wireless communication device, a wireless communication method, and a program capable of contributing to improvement of wireless communication technology related to IDMA. The wireless communication device includes: a wireless communication unit that performs wireless communication using interleave division multiple access (IDMA) with another wireless communication device; and a controller that controls an interleave length in an interleave process for IDMA by the wireless communication unit.

Embodiments include methods, systems and circuits for operating an error trapping logic circuit in a memory device. Aspects include receiving, during a first clock cycle, data and check bits for the data from a memory location and determining, during the first clock cycle, whether the data includes any error by calculating an error syndrome from the data and the check bits. Aspects also include determining, during a second clock cycle, a type of the error based on a full decoding of the error syndrome. Aspects further include determining whether to store the data, the check bits and the error syndrome in trap registers of the error trapping logic circuit based on an operating mode of the error trapping logic circuit and the type of the error.

A storage system and method for handling a burst of errors is provided. In one embodiment, the method comprises generating a protograph using an error code generation method; generating a first partially-lifted protograph based on the generated protograph that avoids a first burst of errors; generating a fully-lifted protograph based on the generated protograph and the generated first partially-lifted protograph; and providing the fully-lifted protograph to a storage system comprising a memory.

A storage system and method for handling a burst of errors is provided. In one embodiment, the method comprises generating a protograph using an error code generation method; generating a first partially-lifted protograph based on the generated protograph that avoids a first burst of errors; generating a fully-lifted protograph based on the generated protograph and the generated first partially-lifted protograph; and providing the fully-lifted protograph to a storage system comprising a memory.

A method and apparatus for estimating a burst error. A burst error estimation method includes measuring a frequency of a spectrum null for an optical signal received through an optical receiver; determining whether the measured frequency of the spectrum null corresponds to an intermediate frequency of a baud rate; and estimating that a burst error occurrence condition is met when the frequency of the spectrum null is determined to correspond to the intermediate frequency of the baud rate.

A method and apparatus for estimating a burst error. A burst error estimation method includes measuring a frequency of a spectrum null for an optical signal received through an optical receiver; determining whether the measured frequency of the spectrum null corresponds to an intermediate frequency of a baud rate; and estimating that a burst error occurrence condition is met when the frequency of the spectrum null is determined to correspond to the intermediate frequency of the baud rate.

A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 3/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for quadrature phase shift keying (QPSK) modulation.