Patent classifications
H03M13/2912
Tiered error correction code (ECC) operations in memory
Apparatuses and methods for performing an error correction code (ECC) operation are provided. One example method can include performing a first error code correction (ECC) operation on a portion of data, performing a second ECC operation on the portion of data in response to the first ECC operation failing, and performing a third ECC operation on the portion of data in response to the second ECC operation failing.
ERROR CORRECTION CIRCUIT, OPERATING METHOD THEREOF AND DATA STORAGE DEVICE INCLUDING THE SAME
An error correction circuit includes a control unit configured to receive a data chunk including data blocks, each of the data blocks being included in corresponding codewords of first and second directions; and a decoder configured to perform a decoding operation for a codeword selected by the control unit. The control unit selects a first codeword among codewords selected in the data chunk, and provides the first codeword to the decoder by performing a flip operation in a first data block included in the first codeword. The control unit selects a second codeword among the selected codewords, and provides the second codeword to the decoder by performing a flip operation in a second data block included in the second codeword. When a decoding operation for the first codeword fails, the control unit selects the second data block to be included in different codewords from the first data block.
DATA STORAGE DEVICE AND OPERATING METHOD THEREOF
A data storage device includes a nonvolatile memory device configured to store a codeword; and a controller configured to read the codeword from the nonvolatile memory device, and perform a decoding process for the codeword, wherein, when performing the decoding process, the controller calculates a flag of the codeword, calculates an expected number of errors by applying an adjustment coefficient to the flag, compares the expected number of errors to an allowed number of errors, and skips or performs a decoding operation for the codeword depending on a comparison result.
High bit rate media FEC recovery
Approaches for recovering one or more media datagrams. A plurality of media datagrams, a plurality of row forward error correction (FEC) datagrams, and a plurality of column FEC datagrams are received. The plurality of media datagrams is logically arranged in rows and columns of media datagrams. Each row FEC datagram corresponds to one of the rows of the media datagrams and each column FEC datagram corresponds to one of the columns of media datagrams. Each received datagram is stored in a buffer. Upon determining that a particular media datagram is missing, it is determined whether a particular row FEC datagram or a particular column FEC datagram covering the particular media datagram has been received and is missing only a single media datagram for which it covers. If so, then, the particular media datagram is recovered using the particular row FEC datagram or the particular column FEC datagram.
TIERED ERROR CORRECTION CODE (ECC) OPERATIONS IN MEMORY
Apparatuses and methods for performing an error correction code (ECC) operation are provided. One example method can include performing a first error code correction (ECC) operation on a portion of data, performing a second ECC operation on the portion of data in response to the first ECC operation failing, and performing a third ECC operation on the portion of data in response to the second ECC operation failing.
Decoding method, memory controlling circuit unit and memory storage device
A decoding method, a memory controlling circuit unit and a memory storage device are provided. The decoding method includes: performing a first type decoding operation for a first frame including a first codeword to obtain a second codeword. The method also includes: recording error estimate information corresponding to the first frame according to an execution result of the first type decoding operation. The method further includes: updating the first codeword in the first frame to the second codeword if the error estimate information matches a first condition; and performing a second type decoding operation for a block code including the first frame.
Memory system and method of operating the memory system
A method of operating a memory system includes receiving information data corresponding to a second program unit that is a part of a first program unit and a write request for the information data from a host; generating a codeword by performing error correction code (ECC) encoding on the received information data such that a partial parity bit corresponding to the information data among all parity bits of the codeword is updated; and providing a memory device with the generated codeword and a write command regarding the codeword.
Flash memory system and operating method thereof
An operation method of a flash memory system includes a hard decision decoding on a codeword and a soft decision decoding on an error message block. The hard decision decoding on a codeword and the codeword comprises message blocks encoded with row constituent codes and column constituent codes according to a block-wise concatenated BCH (BC-BCH) method. When the hard decision decoding fails, the error message block to which the hard decision decoding fails among a plurality of the message blocks is identified. Soft decision information corresponding to the row constituent codes and the column constituent codes of the error message block is generated and the soft decision decoding on the error message block based on the soft decision information is performed.
Concatenated error correction device
A concatenated error correction device may be provided that includes: a first encoder which encodes a plurality of blocks arranged in a column direction and a row direction into a block-wise product code consisting of column codes and row codes by applying a first error correction code to the blocks in each of the column direction and the row direction; and a second encoder which receives K number of source symbols and applies a second error correction code to the source symbols, and then encodes into N number of symbols including N-K number of parity symbols. The N number of symbols form the plurality of blocks. K and N are natural numbers.
Flash memory system and operating method thereof
An operation method of a flash memory system includes: obtaining first syndrome values to a codeword; obtaining locations of errors and the number of the locations of errors based on the first syndrome values; error-correcting the codeword by flipping bit values of error bits of the codeword based on the locations of errors to generate an error-corrected codeword; obtaining second syndrome values to the error-corrected codeword; determining whether an error is found in the error-corrected codeword based on the second syndrome values; changing the first syndrome values when it is determined that no error is found in the error-corrected codeword; and restoring the error-corrected codeword to the codeword by re-flipping the flipped bit values when it is determined that an error is found in the error-corrected codeword.