A computer-implemented method for error-correction-encoding and encrypting of a file is provided. The file is split into at least two blocks. The first block is encrypted using a given encryption key. The encrypted first block is encoded twice using a first and second forward error correction code of the first block. Each subsequent block is encrypted by performing an algebraic operation. The encrypted block is encoded twice using a first and second forward error correction code for this block, wherein a cryptographic indexing function provides a set of indices used by the second forward error correction code to produce the second encoded chunk. The first encoded chunks of each encrypted block are outputted. The computer-implemented method enables secure transmission of a file content between low power devices.

Systems and methods for decoding block and concatenated codes are provided. These include advanced iterative decoding techniques based on belief propagation algorithms, with particular advantages when applied to codes having higher density parity check matrices such as iterative soft-input soft-output and list decoding of convolutional codes, Reed-Solomon codes and BCH codes. Improvements are also provided for performing channel state information estimation including the use of optimum filter lengths based on channel selectivity and adaptive decision-directed channel estimation. These improvements enhance the performance of various communication systems and consumer electronics. Particular improvements are also provided for decoding HD radio signals, satellite radio signals, digital audio broadcasting (DAB) signals, digital audio broadcasting plus (DAB+) signals, digital video broadcasting-handheld (DVB-H) signals, digital video broadcasting-terrestrial (DVB-T) signals, world space system signals, terrestrial-digital multimedia broadcasting (T-DMB) signals, and China mobile multimedia broadcasting (CMMB) signals. These and other improvements enhance the decoding of different digital signals.

A memory device includes a memory array, a processor, and a decoding apparatus. The processor is coupled to the memory array and configured to read encoded data from the memory array. The encoded data includes a plurality of data blocks and each data block is included in two or more data codewords. Further, data codewords belonging to a same pair of data codewords share a common data block. The decoding apparatus is configured to iteratively decode data codewords using hard decoding and soft decoding, and to correct stuck errors by identifying failed data blocks based on shared blocks between failed data codewords.

A hybrid type iterative decoding method for a three-dimensional turbo product code (TPC) having a first axis (FA), a second axis (SA), and a third axis (TA) including: a parallel decoding step of applying a predetermined decoding algorithm (PDA) in parallel to current FA and SA input values (IVs) which are determined based on at least two previous decoding values (DVs), respectively, among the previous FA, SA and TA DVs which are generated in advance to generate a current FA DV and a current SA DV, respectively; a serial decoding step of applying PDA to a current TA IV determined based on the current FA and SA DVs to generate a current TA DV; and performing hard decision based on the current FAs DV, the current SA DV, the current TA DV, and the received signal value.

An error correction circuit includes a control unit configured to receive a data chunk including data blocks, each of the data blocks being included in corresponding codewords of first and second directions; and a decoder configured to perform a decoding operation for a codeword selected by the control unit. The control unit selects a first codeword among codewords selected in the data chunk, and provides the first codeword to the decoder by performing a flip operation in a first data block included in the first codeword. The control unit selects a second codeword among the selected codewords, and provides the second codeword to the decoder by performing a flip operation in a second data block included in the second codeword. When a decoding operation for the first codeword fails, the control unit selects the second data block to be included in different codewords from the first data block.

A memory system may include: a memory device including a plurality of pages for storing data and a plurality of memory blocks including the pages; and a controller configured to read data, which corresponds to a read command received from a host, from the pages, perform bit flipping with respect to a plurality of constituent codes for the read data, and perform an error correction operation, the bit flipping is updated corresponding to a number of error correction bits in the constituent codes.

There is provided an ultra-light decoder for high speed digital communications based on block codes such as turbo product codes (TPCs). The new decoder can perform soft decision decoding without an algebraic hard decision decoder, which is the core of conventional soft decision decoders. The elimination of algebraic decoder significantly reduces the number of computations required per codeword, consequently, it reduces the decoding delay and processing power. However, reducing the decoding delay would immediately enable increasing the transmission speed, and minimize the need for large buffers at the receiver. Moreover, reducing the complexity and delay would enable using codes with high code rates to increase the system capacity, or use powerful codes with low code rates to reduce the transmission power. Such benefits can be achieved for about 1 dB loss in coding gain. There is also provided a receiver comprising the ultra-light decoder, as well as a decoding process.

Embodiments of the present disclosure provide a high speed low latency rate configurable soft decision and hard decision based pipelined Reed-Solomon (RS) decoder architecture suitable for optical communication and storage. The proposed RS decoder is a configurable RS decoder that is configured to monitor the channel and adjust code parameters based on channel capacity. The proposed RS decoder includes interpolation and factorization free Low-Complexity-Chase (LCC) decoding to implement soft-decision decoder (SDD). The proposed RS decoder generates test vectors and feeds these to a pipelined 2-stage hard decision decoder (HDD). The proposed RS decoder architecture computes error locator polynomial in exactly 2t clock cycles without parallelism and supports high throughput, and further computes error evaluator polynomial in exactly t cycles. The present disclosure provides a 2-stage pipelined decoder to operate at least latency possible and reduced size of delay buffer.

Disclosed is a three-dimensional TPC decoding apparatus. A three-dimensional TPC decoding apparatus includes an X decoder which decodes an X axis of an m-th upper half layer based on decoding results of a Y axis and a Z axis of an m1-th upper half layer; a Y decoder which decodes a Y axis of an m-th lower half layer based on decoding results of an X axis and a Z axis of an m1-th lower half layer; and a Z decoder which decodes a Z axis based on a decoding result of the Y axis of an m-th upper half layer and a decoding result of the X axis of an m-th lower half layer.

Techniques are described for decoding a first message. In one example, the techniques include obtaining a second message comprising reliability information corresponding to each bit in the first message, performing a soft decision decoding procedure on the second message to generate a decoded codeword, wherein the soft decision decoding procedure comprises a joint decoding and miscorrection avoidance procedure, and outputting the decoded codeword.