A decoder controller may be provided. The decoder controller may include flip number management section configured to, after a decoding operation for a codeword of a first direction succeeds, decrease flip numbers of all codewords of a second direction which intersect with the codeword of the first direction and have error-probable areas.

Systems and methods for decoding block and concatenated codes are provided. These include advanced iterative decoding techniques based on belief propagation algorithms, with particular advantages when applied to codes having higher density parity check matrices such as iterative soft-input soft-output and list decoding of convolutional codes, Reed-Solomon codes and BCH codes. Improvements are also provided for performing channel state information estimation including the use of optimum filter lengths based on channel selectivity and adaptive decision-directed channel estimation. These improvements enhance the performance of various communication systems and consumer electronics. Particular improvements are also provided for decoding HD radio signals, satellite radio signals, digital audio broadcasting (DAB) signals, digital audio broadcasting plus (DAB+) signals, digital video broadcasting-handheld (DVB-H) signals, digital video broadcasting-terrestrial (DVB-T) signals, world space system signals, terrestrial-digital multimedia broadcasting (T-DMB) signals, and China mobile multimedia broadcasting (CMMB) signals. These and other improvements enhance the decoding of different digital signals.

An application specific integrated circuit (ASIC) tangibly encodes a program of instructions executable by the integrated circuit to perform a method for fast Chase decoding of generalized Reed-Solomon (GRS) codes. The method includes using outputs of a syndrome-based hard-decision (HD) algorithm to find an initial Groebner basis G for a solution module of a key equation, upon failure of HD decoding of a GRS codeword received by the ASIC from a communication channel; traversing a tree of error patterns on a plurality of unreliable coordinates to adjoin a next weak coordinate, where vertices of the tree of error patterns correspond to error patterns, and edges connect a parent error pattern to a child error pattern having exactly one additional non-zero value, to find a Groebner basis for each adjoining error location; and outputting an estimated transmitted codeword when a correct error vector has been found.

An error correction circuit includes a control unit configured to receive a data chunk including data blocks, each of the data blocks being included in corresponding codewords of first and second directions; and a decoder configured to perform a decoding operation for a codeword selected by the control unit. The control unit selects a first codeword among codewords selected in the data chunk, and provides the first codeword to the decoder by performing a flip operation in a first data block included in the first codeword. The control unit selects a second codeword among the selected codewords, and provides the second codeword to the decoder by performing a flip operation in a second data block included in the second codeword. When a decoding operation for the first codeword fails, the control unit selects the second data block to be included in different codewords from the first data block.

Techniques for reducing the latency for decoding product codewords with minimal hardware architecture changes are described. In an example, a system accesses and decodes a generalized product code (GPC) codeword by using at least one of a plurality of Chase decoding procedures available on the system. A first Chase decoding procedure is configured according to first values for a set of decoding parameters. A second Chase decoding procedure is configured according to second values for the set of decoding parameters. The second values are different from the first values. The first Chase decoding procedure has a smaller latency and a higher bit error rate (BER) relative to the second Chase decoding procedure based on the first values and the second values for the set of decoding parameters.

Techniques for reducing the latency for decoding product codewords with minimal hardware architecture changes are described. In an example, multiple decoding procedures are available a system. The system maintains decoding states. Each decoding state corresponds to a constituent codeword of a product codeword and to a decoding procedure. For instance, a BCH decoding state indicates whether the decoding of the respective BCH constituent codeword has previously failed. The decoding of the product codeword depends on the various decoding state. For instance, in a BCH decoding iteration, if a BCH decoding state of a constitutent codeword is set to failed, the BCH decoding of that codeword is skipped.

Systems and methods for decoding block and concatenated codes are provided. These include advanced iterative decoding techniques based on belief propagation algorithms, with particular advantages when applied to codes having higher density parity check matrices such as iterative soft-input soft-output and list decoding of convolutional codes, Reed-Solomon codes and BCH codes. Improvements are also provided for performing channel state information estimation including the use of optimum filter lengths based on channel selectivity and adaptive decision-directed channel estimation. These improvements enhance the performance of various communication systems and consumer electronics. Particular improvements are also provided for decoding HD radio signals, satellite radio signals, digital audio broadcasting (DAB) signals, digital audio broadcasting plus (DAB+) signals, digital video broadcasting-handheld (DVB-H) signals, digital video broadcasting-terrestrial (DVB-T) signals, world space system signals, terrestrial-digital multimedia broadcasting (T-DMB) signals, and China mobile multimedia broadcasting (CMMB) signals. These and other improvements enhance the decoding of different digital signals.

There is provided an ultra-light decoder for high speed digital communications based on block codes such as turbo product codes (TPCs). The new decoder can perform soft decision decoding without an algebraic hard decision decoder, which is the core of conventional soft decision decoders. The elimination of algebraic decoder significantly reduces the number of computations required per codeword, consequently, it reduces the decoding delay and processing power. However, reducing the decoding delay would immediately enable increasing the transmission speed, and minimize the need for large buffers at the receiver. Moreover, reducing the complexity and delay would enable using codes with high code rates to increase the system capacity, or use powerful codes with low code rates to reduce the transmission power. Such benefits can be achieved for about 1 dB loss in coding gain. There is also provided a receiver comprising the ultra-light decoder, as well as a decoding process.

A hybrid type iterative decoding method for a three-dimensional turbo product code (TPC) having a first axis (FA), a second axis (SA), and a third axis (TA) including: a parallel decoding step of applying a predetermined decoding algorithm (PDA) in parallel to current FA and SA input values (IVs) which are determined based on at least two previous decoding values (DVs), respectively, among the previous FA, SA and TA DVs which are generated in advance to generate a current FA DV and a current SA DV, respectively; a serial decoding step of applying PDA to a current TA IV determined based on the current FA and SA DVs to generate a current TA DV; and performing hard decision based on the current FAs DV, the current SA DV, the current TA DV, and the received signal value.

Disclosed is a three-dimensional TPC decoding apparatus. A three-dimensional TPC decoding apparatus includes an X decoder which decodes an X axis of an m-th upper half layer based on decoding results of a Y axis and a Z axis of an m1-th upper half layer; a Y decoder which decodes a Y axis of an m-th lower half layer based on decoding results of an X axis and a Z axis of an m1-th lower half layer; and a Z decoder which decodes a Z axis based on a decoding result of the Y axis of an m-th upper half layer and a decoding result of the X axis of an m-th lower half layer.