A wiring board includes a first wire, a second wire, a third wire and a fourth wire formed over a substrate and extending in a first direction respectively, the second wire being adjacent to the first wire in the first direction, and the third wire being adjacent to the first wire in a second direction orthogonal to the first direction, and the fourth wire being adjacent to the second wire in the second direction, a pair of fifth wires, a pair of sixth wires, a pair of seventh wires and a pair of eighth wires formed in the substrate and extending in the second direction respectively, a pair of ninth signal vias, a pair of tenth signal vias, a pair of eleventh signal vias and a pair of twelfth signal vias formed in the substrate and extending in a third direction orthogonal to a surface of the substrate respectively.

A quadrature detection unit subjects an FM signal to quadrature detection using a local oscillation signal and outputs a base band signal. A first correction unit and a second correction unit correct the base band signal using a DC offset correction value. A DC offset detection unit subjects the corrected base band signal to rectangular to polar conversion and derives the DC offset correction value such that amplitudes in a plurality of phase domains defined in an IQ plane approximate each other. An FM detection unit subjects the corrected base band signal to FM detection and generates a detection signal. An addition unit adds an offset to the detection signal. An AFC unit generates a control signal for controlling a frequency of a local oscillation signal based on the detection signal to which the offset is added.

A circuit for direct current (DC) offset estimation comprises a quantile value circuit and a signal processor. The quantile value circuit determines a plurality of quantile values of an input signal and includes a plurality of quantile filters. Each quantile filter includes a comparator, a level shifter, a monotonic transfer function component, and a latched integrator. The comparator compares the input signal and a quantile value. The level shifter shifts the output of the comparator. The monotonic transfer function component determines the magnitude of the shifted signal and provide a transfer function signal. The latched integrator suppresses transient characteristics of the transfer function signal and provide the quantile value. The signal processor is configured to calculate a weighted average of the quantile values to yield a DC offset estimate.

A receiver circuit includes an analog-to-digital converter (ADC), a decision feedback equalizer (DFE), a slicer, and a timing error detector (TED). The DFE is coupled to the ADC, and includes a first tap and a second tap. The slicer is coupled to the DFE. The TED is coupled to the slicer. The TED is configured to initialize timing of a sampling clock provided to the ADC while initializing the second tap of the DFE and holding the first tap of the DFE at a constant value.

A circuit for direct current (DC) offset estimation comprises a quantile value circuit and a signal processor. The quantile value circuit determines a plurality of quantile values of an input signal and includes a plurality of quantile filters. Each quantile filter includes a comparator, a level shifter, a monotonic transfer function component, and a latched integrator. The comparator compares the input signal and a quantile value. The level shifter shifts the output of the comparator. The monotonic transfer function component determines the magnitude of the shifted signal and provide a transfer function signal. The latched integrator suppresses transient characteristics of the transfer function signal and provide the quantile value. The signal processor is configured to calculate a weighted average of the quantile values to yield a DC offset estimate.

A method for operating a radio frequency communications system includes, while operating a first radio frequency communications device in a calibration mode, for each setting of a plurality of settings of a programmable gain amplifier in a receiver of the first radio frequency communications device configured in a zero-intermediate frequency mode of operation, generating an estimate of a DC offset in each of a plurality of digital samples received from an analog circuit path including the programmable gain amplifier, and storing in a corresponding storage element, a compensation value based on the estimate.

A radio system comprises a radio transmitter apparatus and a radio receiver apparatus. The radio transmitter apparatus is configured to transmit a continuous-wave radio-frequency signal having a first frequency. The radio receiver apparatus comprises: an antenna for receiving the continuous-wave radio-frequency signal; a local oscillator for generating a periodic signal at a second frequency which differs from the first frequency by a frequency offset; a mixer for mixing the received continuous-wave radio-frequency signal with the periodic signal to generate a down-mixed signal; and a processor or other circuitry configured to generate frequency-offset data from the down-mixed signal, wherein the frequency-offset data is representative of an estimate of the frequency offset. The processor or other circuitry is configured to use the frequency-offset data to generate DC-offset data representative of an estimate of a DC offset component of the down-mixed signal.

A method for operating a radio frequency communications system includes, while operating a first radio frequency communications device in a calibration mode, for each setting of a plurality of settings of a programmable gain amplifier in a receiver of the first radio frequency communications device configured in a zero-intermediate frequency mode of operation, generating an estimate of a DC offset in each of a plurality of digital samples received from an analog circuit path including the programmable gain amplifier, and storing in a corresponding storage element, a compensation value based on the estimate.

A radio frequency, RF, transmitter, comprises a digitally controlled oscillator, DCO, configured to generate an RF signal; and digital modulation circuitry connected to the DCO for modulation of the RF signal, and driven by an RF clock signal derived from the RF signal, wherein the digital modulation circuitry comprises a module configured to apply a compensation for modulation jitter due to the modulation circuitry being driven by the RF clock signal and a compensation for DCO non-linearity.

A circuit for direct current (DC) offset estimation comprises a quantile value circuit and a signal processor. The quantile value circuit determines a plurality of quantile values of an input signal and includes a plurality of quantile filters. Each quantile filter includes a comparator, a level shifter, a monotonic transfer function component, and a latched integrator. The comparator compares the input signal and a quantile value. The level shifter shifts the output of the comparator. The monotonic transfer function component determines the magnitude of the shifted signal and provide a transfer function signal. The latched integrator suppresses transient characteristics of the transfer function signal and provide the quantile value. The signal processor is configured to calculate a weighted average of the quantile values to yield a DC offset estimate.