A wiring board includes a first wire, a second wire, a third wire and a fourth wire formed over a substrate and extending in a first direction respectively, the second wire being adjacent to the first wire in the first direction, and the third wire being adjacent to the first wire in a second direction orthogonal to the first direction, and the fourth wire being adjacent to the second wire in the second direction, a pair of fifth wires, a pair of sixth wires, a pair of seventh wires and a pair of eighth wires formed in the substrate and extending in the second direction respectively, a pair of ninth signal vias, a pair of tenth signal vias, a pair of eleventh signal vias and a pair of twelfth signal vias formed in the substrate and extending in a third direction orthogonal to a surface of the substrate respectively.

The present disclosure relates to a communication method and system for converging a 5.sup.th-Generation (5G) communication system for supporting higher data rates beyond a 4.sup.th-Generation (4G) system with a technology for Internet of Things (IoT). The present disclosure may be applied to intelligent services based on the 5G communication technology and the IoT-related technology, such as smart home, smart building, smart city, smart car, connected car, health care, digital education, smart retail, security and safety services.

There may be provided a method for receiving a downlink by a UE that uses narrowband communication and a UE for performing the same, the method comprising the steps of: setting one subcarrier, among narrowband frequency resources assigned to the UE, as a narrowband direct current (DC) subcarrier; receiving a signal regarding the narrowband frequency resources from an eNB; and decoding the received signal on the basis of the narrowband DC subcarrier that has been set.

The present invention relates to a method and an apparatus for direct current offset calibration of a direct conversion receiver, a Direct Current (DC) offset calibration apparatus of a direct conversion receiver includes a plurality of variable gain amplifiers for amplifying an input signal based on a gain control value, a DC offset monitoring unit for monitoring a DC offset for an output signal of the plurality of variable gain amplifiers, a plurality of variable Digital to Analog Converters (DACs) for controlling a current applied to each of the plurality of variable gain amplifiers according to a current control code, and a DC offset cancellation unit for determining a current control code set which minimizes the DC offset value per preset gain control value, and thus the DC offset can be precisely cancelled without being affected by external factors such as a signal modulation method and heat and performance degradation of the receiver can be prevented.

After transmitting first electrical signals to a receiver, a transmitter receives a burst absent mode signal from the receiver. While in a ready state, the transmitter receives a signal including a data burst, converts the signal to second electrical signals, including a settled DC offset, and transmits the second electrical signals to the receiver. The receiver transmits the burst absent mode signal to the transmitter after receiving the first electrical signals, detects a presence of the second electrical signals. In response to detecting the presence of the second electrical signals, the receiver removes the DC offset from the second electrical signals to generate output signals, and causes transmitting the output signals to a subsequent device. The receiver removes the DC offset by causing an instruction to discharge AC coupling capacitors. The burst absent mode signal is generated using a host reset instruction or an internally generated instruction.

A device for determining a DC component in a zero-IF radio receiver comprises an input configured to receive a complex baseband signal; and an analyzer configured to analyze the complex baseband signal to determine a DC component in the complex baseband signal by selecting at least three samples of the complex baseband signal and determining the intersection of at least two perpendicular bisectors of at least two straight lines, each straight line running through a different pair of two of said selected samples, said intersection representing the DC component. Further, a corresponding method, a radar device and a radar method are disclosed.

The present disclosure relates to a wireless communication node comprising at least one array antenna configured to receive a radio signal, said array antenna comprising a plurality of receiving antenna devices, each of said antenna devices being connected to a respective receiving circuit which is configured for processing said radio signal. Each receiving circuit comprises a demodulator, an analog-to-digital converter and a decoder, the demodulator being configured to receive an analog signal from the corresponding receiving antenna device and to output a demodulated analog signal to said analog-to-digital converter which outputs a converted digital signal to the decoder. Furthermore, the node is configured for adding a direct current, DC, offset value to said demodulated analog signal wherein the combined offset values of said node follow a predetermined distribution of values, having a variance, over the analog-to-digital converters.

Techniques are disclosed relating to DC interference cancelation in received wireless signals. Disclosed techniques may be performed in the digital domain, in conjunction with analog cancelation techniques. In some embodiments, a receiver apparatus operates a local oscillator at a frequency corresponding to a particular pilot symbol in a received wireless signal. In some embodiments the receiver estimates DC interference at the frequency based on the received pilot symbol (this may be facilitated by the fact that the contents of pilot symbols are known, because they are typically used for channel estimation). In some embodiments, the receiver apparatus is configured to cancel the DC interference based on the estimate to determine received data in subsequently received signals at the frequency. Disclosed techniques may allow narrowband receivers to efficiently use more of their allocated frequency bandwidth, rather than wasting bandwidth near the frequency of the local oscillator.

An embodiment method includes measuring, by a calibration device, a first output voltage of a variable gain amplifier (VGA) when the VGA is set at a first gain setting and measuring, by a calibration device, a second output voltage of the VGA when the VGA is set at a second gain setting different from the first gain setting. The method further includes calculating, by the calibration device, an offset voltage of a signal path including the VGA using the first output voltage and the second output voltage and calculating, by the calibration device, an internal offset voltage of the VGA using the first output voltage and the second output voltage.

An embodiment method includes measuring, by a calibration device, a first output voltage of a variable gain amplifier (VGA) when the VGA is set at a first gain setting and measuring, by a calibration device, a second output voltage of the VGA when the VGA is set at a second gain setting different from the first gain setting. The method further includes calculating, by the calibration device, an offset voltage of a signal path including the VGA using the first output voltage and the second output voltage and calculating, by the calibration device, an internal offset voltage of the VGA using the first output voltage and the second output voltage.

One example includes a super-lattice castellated field effect transistor (SLCFET) system. The system includes a plurality of SLCFETs arranged in a series stack between a first port and a second port to provide a propagation path of a radio frequency (RF) signal between the first port and the second port in response to activation of the SLCFETs. The system also includes a plurality of gate resistors interconnecting gate terminals associated with each of the respective SLCFETs and an activation port to which an activation signal is provided to concurrently activate the SLCFETs. The system further includes a plurality of balancing resistors coupled to the gate terminals associated with each of the respective SLCFETs, the balancing resistors being configured to approximately equalize a drain-gate voltage and a gate-source voltage associated with each of the SLCFETs when activated.