A high-frequency switch circuit includes a first switch configured to electrify or cut off connection between an antenna terminal and an input terminal, and a second switch configured to electrify or cut off connection between the antenna terminal and an output terminal. The first switch has a transmission line connecting the antenna terminal and the input terminal; a diode having an anode connected to a first node between the transmission line and the input terminal, and a cathode connected to a second node; and a capacitor connected to the second node and a first power supply voltage. A first control terminal is connected to the first node via a first resistor and a first inductor. The first switch further includes a charging/discharging circuit connected to a second power supply voltage and the first control terminal and charging and discharging the capacitor from the second node.

Input circuitry for an analog-to-digital converter (ADC) is provided. The input circuitry includes a calibration signal source configured to output a calibration signal for the ADC and an analog circuitry configured to receive and process an analog input signal for the ADC. The analog circuitry is further configured to generate a combined signal by combining the analog input signal and the calibration signal. The input circuitry further includes a buffer amplifier coupled to the analog circuitry and configured to supply a buffered signal to the ADC based on the combined signal. Further, the input circuitry includes neutralization circuitry configured to generate, based on the calibration signal, a neutralization signal for mitigating an unwanted signal component related to a limited reverse isolation of the analog circuitry. The neutralization circuitry is further configured to supply the neutralization signal to at least one of an input node and an intermediate node of the analog circuitry.

Input circuitry for an analog-to-digital converter (ADC) is provided. The input circuitry includes a calibration signal source configured to output a calibration signal for the ADC and an analog circuitry configured to receive and process an analog input signal for the ADC. The analog circuitry is further configured to generate a combined signal by combining the analog input signal and the calibration signal. The input circuitry further includes a buffer amplifier coupled to the analog circuitry and configured to supply a buffered signal to the ADC based on the combined signal. Further, the input circuitry includes neutralization circuitry configured to generate, based on the calibration signal, a neutralization signal for mitigating an unwanted signal component related to a limited reverse isolation of the analog circuitry. The neutralization circuitry is further configured to supply the neutralization signal to at least one of an input node and an intermediate node of the analog circuitry.

This disclosure provide various techniques for improving the quality of a signal. By integrating phase-shifting circuitry with a transmit/receive (T/R) switch, insertion loss may be reduced while decreasing space consumed on an integrated circuit or printed circuit board. In particular, embodiments disclosed herein include a transmitter and a receiver, each including one or more differential amplifiers coupled to a first inductor, and a switching network coupled to a second inductor and one or more phase-shifting circuitries. A differential interface of the differential amplifiers may enable integration of a stage of the phase shifter (e.g., a 180 degree stage) with the T/R switch, such that a single circuit may operate as the phase shifter and the T/R switch. This implementation may reduce the number of T/R switches and phase shifter stages in the phased array system, reducing the overall insertion loss experienced by the phased array system.

A transceiver interface for a phased array element includes a first magnetic circuit having a primary coil and a secondary coil, a second magnetic circuit having a primary coil, a secondary coil and a tertiary coil, a main amplifier path and an auxiliary amplifier path, the main amplifier path coupled to the primary coil of the second magnetic circuit and configured to receive a quadrature signal, the main amplifier path configured to provide a quadrature output signal, the auxiliary amplifier path coupled to the primary coil of the first magnetic circuit and configured to receive an in-phase signal, the auxiliary amplifier path configured to provide an in-phase output signal, a selectable output circuit configured to selectively combine the in-phase output signal and the quadrature output signal, and a low noise amplifier (LNA) coupled to the tertiary coil of the second magnetic circuit.

A circuit for downlink/uplink operational mode switching in a TDD wireless communication system comprises a field-effect transistor operatively connected to a power amplifier on the downlink path of a RF front-end apparatus in a TDD wireless communication system, a first voltage generator connected to a large-value first resistor, a second voltage generator connected to a second resistor, a large-value hold capacitor, and a sample-and-hold circuit configured to be switched between a reception configuration, wherein the first voltage generator is connected to the gate of the field-effect transistor and the large-value capacitor is connected to the first voltage generator through the first resistor, and a transmission configuration, wherein the gate of the field-effect transistor is connected to the hold capacitor and the hold capacitor is connected to the second voltage generator through the second resistor.

A circuit for downlink/uplink operational mode switching in a TDD wireless communication system comprises a field-effect transistor operatively connected to a power amplifier on the downlink path of a RF front-end apparatus in a TDD wireless communication system, a first voltage generator connected to a large-value first resistor, a second voltage generator connected to a second resistor, a large-value hold capacitor, and a sample-and-hold circuit configured to be switched between a reception configuration, wherein the first voltage generator is connected to the gate of the field-effect transistor and the large-value capacitor is connected to the first voltage generator through the first resistor, and a transmission configuration, wherein the gate of the field-effect transistor is connected to the hold capacitor and the hold capacitor is connected to the second voltage generator through the second resistor.

An antenna module includes a dielectric substrate and a radiation element disposed on the dielectric substrate. The dielectric substrate includes a flat portion (131) and a flat portion (130) having mutually different normal directions, and a bent portion connecting the flat portion (131) and the flat portion (130) to each other. The flat portion (131) has a protruding portion partially protruding in a direction toward the flat portion (130) along the flat portion (131) from a boundary portion between the bent portion and the flat portion (131). The flat portion (131) and the bent portion are connected to each other at a position where the protruding portion is not provided in the flat portion (131). At least a part of the radiation element is disposed on the protruding portion.

A network device includes a transceiver configured to concurrently transmit signals and receive signals within a single frequency band resulting in radio-frequency signal interference. The device includes an analog canceler configured to mitigate the signal interference. The device includes a neural network that receives data that describes characteristics of the signal interference and provides coefficients for the analog canceler as outputs. The neural network-generated coefficients are applied to the analog canceler which uses them to cancel the signal interference.

A radio-frequency module includes a switch performing switching of the connection between a common terminal and a selection terminal, a reception filter having a reception band in a band A as a passband, a transmission filter that has a transmission band in a band B as a passband and has an output terminal connected to the selection terminal, a filter that has the transmission band in a band B as an attenuation band and has an input terminal connected to the selection terminal, a reception path which connects the selection terminal and an input terminal of the reception filter and on which the filter is disposed, a bypass path which connects the selection terminal and the input terminal of the reception filter and on which no filter is disposed, and a transmission path which connects the selection terminal and a transmission terminal and on which the transmission filter is disposed.