H04B3/235

High-speed receiver architecture

A receiver (e.g., for a 10G fiber communications link) includes an interleaved ADC coupled to a multi-channel equalizer that can provide different equalization for different ADC channels within the interleaved ADC. That is, the multi-channel equalizer can compensate for channel-dependent impairments. In one approach, the multi-channel equalizer is a feedforward equalizer (FFE) coupled to a Viterbi decorder, for example, a sliding block Viterbi decoder (SBVD); and the FFE and/or the channel estimator for the Viterbi decoder are adapted using the LMS algorithm.

COMMUNICATION DEVICE AND ECHO CANCELLATION METHOD THEREOF
20190245673 · 2019-08-08 · ·

A communication device and an echo cancellation method are provided. A digital echo canceller is coupled to a transmitting circuit and a receiving circuit to generate an echo energy indicator according to a digital output signal and a digital input signal. A transceiving front-end circuit receives the analog output signal and generates a hybrid interface signal. A hybrid fine-tune circuit generates a first and a second capacitance calibration signals according to the echo energy indicator. An analog echo cancellation circuit receives the first and second capacitance calibration signals, and includes a first and a second variable capacitors controlled by the first capacitance calibration signal and a third and a fourth variable capacitors controlled by the second capacitance calibration signal. The analog echo cancellation circuit receives the analog output signal and the hybrid interface signal, and generates the analog input signal according to the first and second capacitance calibration signals.

Adaptive filter with manageable resource sharing
10367545 · 2019-07-30 · ·

The present application relates to an adaptive filter using manageable resource sharing and a method of operating the adaptive filter. The adaptive filter comprises a cluster controller configured for allocating each of several computational blocks to one of several clusters and a routing controller for configuring the routing of tapped delay signals by a routing logic to the respective cluster in accordance with an allocation of the tapped delay signals to the clusters. Each of computational blocks is configured for adjusting one filter coefficient, c.sub.i(n), in one cycle of an iterative procedure according to an adaptive convergence algorithm. The number of computational blocks is less than an order of the adaptive filter.

Ethernet Transceiver with PHY-Level Signal-Loss Detector
20190165921 · 2019-05-30 ·

An Ethernet transceiver includes physical-layer (PHY) circuitry and a signal-loss detector. The PHY circuitry is configured to receive a signal from a peer transceiver, to process the received signal in a series of digital PHY-level processing operations, and to output the processed signal for Medium Access Control (MAC) processing. The signal-loss detector is configured to receive, from the PHY circuitry, a digital version of the received signal, and to detect a signal-loss event based on an amplitude of the digital version of the received signal.

METHODS AND SYSTEMS FOR UTILIZING LOW GAIN LOW NOISE SIGNAL AMPLIFICATION AND IDEAL TAPS IN COAXIAL NETWORKS
20190081661 · 2019-03-14 ·

Systems and methods are provided for utilizing low gain low noise signal amplification and ideal taps in coaxial networks. An ideal tap configured for use in coaxial networks may have a plurality of ports, one or more processing circuits configured for handling reception and transmission of signals communicated via the tap, and one or more echo cancellation circuits configured for providing echo cancellation during operations of the tap. The processing circuits are configured based on particular predefined tap performance criteria. The tap performance criteria may relate to one or more of port-to-port isolation, return loss, port-to-port gain, and up-tilt. The echo cancellation circuits may be configurable for providing the echo cancellation based on the tap performance criteria. The echo cancellation circuits may include an echo cancellation control circuit for controlling echo cancellation functions and/or operations. The echo cancellation circuits may include dedicated per-port echo cancellation circuits.

HIGH-SPEED RECEIVER ARCHITECTURE

A receiver (e.g., for a 10G fiber communications link) includes an interleaved ADC coupled to a multi-channel equalizer that can provide different equalization for different ADC channels within the interleaved ADC. That is, the multi-channel equalizer can compensate for channel-dependent impairments. In one approach, the multi-channel equalizer is a feedforward equalizer (FFE) coupled to a Viterbi decorder, for example, a sliding block Viterbi decoder (SBVD); and the FFE and/or the channel estimator for the Viterbi decoder are adapted using the LMS algorithm.

Channel quality indicator for wireline channel degradation detection

Systems and techniques relating to channel degradation detection for communication systems are described. A described system includes a processor and an interface to transmit signals and receive signals via a channel that includes a cable. The processor can be configured to perform echo cancellation based on echo tap values to remove portions of the transmitted signals that appear as echoes within the received signals, signal equalization based on equalizer tap values, or both. The processor can be configured to determine a channel quality indicator of the channel based on one or more of the echo tap values, one or more of the equalizer tap values, or both. The processor can be configured to generate a warning indication based on the channel quality indicator indicating a degradation of the cable or the channel.

Interference cancellation in a transceiver device
12063056 · 2024-08-13 · ·

The present disclosure is directed to improvements in interference mitigation for Adjacent Channel Leakage in wireline communication, and more specifically, but not exclusively, to improved kernel designs that can facilitate interference mitigation for Adjacent Channel Leakage in cable modem systems. Examples of the present disclosure provide an apparatus for a transceiver device that comprises interference cancellation circuitry configured to cancel interference caused by upstream signals in one or more upstream sub-bands on one or more downstream sub-bands based on a combination of a plurality of kernels. The interference is at least partially caused by non-linearities within a transmission circuitry of the transceiver device, the plurality of kernels representing the non-linearities within the transmission circuitry of the transceiver device. Each of the kernels comprises one or more associated terms, with each of the associated terms being in-band for at least one of the one or more downstream sub-bands.

DETECTION APPARATUS, DETECTION METHOD, AND DETECTION PROGRAM

A detection apparatus is provided for a signal transmission apparatus, the signal transmission apparatus being configured to receive a reception signal via a transmission line and including an adaptive filter to be applied to the reception signal. The detection apparatus includes an acquisition unit configured to acquire a filter coefficient of the adaptive filter, and a detection unit configured to detect an abnormality in the transmission line, based on an amount of change over time in the filter coefficient acquired by the acquisition unit.

Joint acoustic echo control and adaptive array processing
10129409 · 2018-11-13 · ·

A system and method for joint acoustic echo control and adaptive array processing, comprising the decomposition of a captured sound field into N sub-sound fields, applying linear echo cancellation to each sub-sound field, selecting L sub-sound fields from the N sub-sound fields, performing L channel adaptive array processing utilizing the L selected sub-sound fields, and applying non-linear audio echo cancellation.