Systems and methods for data multiplexing include or use a data serializer having a first set of four serializer outputs and a second set of four serializer outputs. The systems and methods also use or include a pair of 4 to 1 multiplexers each having four first multiplexer inputs and one first multiplexer outputs and a 2 to 1 multiplexer having two multiplexer inputs and one multiplexer output.

An apparatus and a method for sampling a signal in a wireless communication system that employs a time division duplex (TDD) scheme are provided. According to various embodiments of the present disclosure, a method for a base station being operated in a wireless communication system that employs TDD comprises the steps of: determining a switching section for controlling a conversion mode of a sampling rate conversion circuit based on a timing advance (TA) value with respect to a signal transmitted by a terminal; generating a switching signal within the switching section; changing the conversion mode from a first mode to second mode in response to the switching signal; and changing a sampling rate of a transmission signal or reception signal based on the second mode. As a result, the transmission signal and the reception signal can be prevented from overlapping in the sampling rate conversion circuit that can perform both of up conversion and down conversion, and hardware resources for changing a sampling rate of a signal can be reduced.

A baseline difference is determined between a slave line card time stamp corresponding to a slave line card frame sync signal and a master line card time stamp corresponding to a master line card frame sync signal. The slave line card generates subsequent slave line card time stamps for subsequent slave line card frame sync signals and the master line card generates subsequent master line card time stamps for subsequent master line card frame sync signals. Current differences are determined between subsequent slave line card time stamps and the subsequent master line card time stamps and the current differences are compared to the baseline difference. When a mismatch difference occurs (current difference differs from the baseline difference), the mismatch difference causes a phase-locked loop in the master line card to be adjusted or an offset to be provided to the master line card time of day counter.

Systems and methods for data multiplexing include or use a data serializer having a first set of four serializer outputs and a second set of four serializer outputs. The systems and methods also use or include a pair of 4 to 1 multiplexers each having four first multiplexer inputs and one first multiplexer outputs and a 2 to 1 multiplexer having two multiplexer inputs and one multiplexer output.

The apparatus may be a user equipment (UE). The apparatus receives a transmission of at least one of a plurality of first synchronization signals. The apparatus receives at least one repeat transmission of the at least one of the plurality of first synchronization signals. In an aspect, the transmission and the at least one repeat transmission are received in a same synchronization signal block.

An integrated circuit includes a control circuit, a primary sensor device coupled to the control circuit, and a plurality of groups of secondary sensor devices coupled to the primary sensor device. The primary sensor device receives a master clock signal from the control device and outputs, to each group of secondary sensor devices, a respective secondary clock signal with a frequency lower than the primary clock signal. The primary sensor device generates primary sensor data. The primary sensor device receives secondary sensor data from each group of secondary sensor devices. The primary sensor device combines the primary sensor data and all of the secondary sensor data into a sensor data stream with a time division-multiplexing scheme and outputs the sensor data stream to the control circuit.

An integrated circuit includes a control circuit, a primary sensor device coupled to the control circuit, and a plurality of groups of secondary sensor devices coupled to the primary sensor device. The primary sensor device receives a master clock signal from the control device and outputs, to each group of secondary sensor devices, a respective secondary clock signal with a frequency lower than the primary clock signal. The primary sensor device generates primary sensor data. The primary sensor device receives secondary sensor data from each group of secondary sensor devices. The primary sensor device combines the primary sensor data and all of the secondary sensor data into a sensor data stream with a time division-multiplexing scheme and outputs the sensor data stream to the control circuit.

Systems, circuits, and methods for synchronizing devices in the time-domain are provided. A method, according to one implementation, includes determining a round-trip number based on a width of one cycle of a timestamping clock signal. The round-trip number is equal to a plurality of times that a clock signal is to be transmitted in a loop from a timing-leader component to a timing-follower component and back to the timing-leader component. The method also includes utilizing the timestamping clock signal to detect a cumulative time delay that results when the clock signal is transmitted in the loop a number of times equal to the round-trip number. The cumulative time delay is configured to enable synchronization of the timing-follower component with the timing-leader component.

A Biphase Mark Coding (BMC) transceiver is provided. In the BMC transceiver, an operational amplifier operating in a time division multiplexing manner is used. The operational amplifier is configured as a unity gain buffer, and it is determined whether the BMC transceiver operates as a transmitter or a receiver by selecting different input switches and output switches. In a transmitting mode, a bias current of an input differential pair transistor of the operational amplifier is changed, to change a slew rate, so as to obtain an output waveform with adjustable rising/falling edges of the transmitter.

An integrated circuit includes a control circuit, a primary sensor device coupled to the control circuit, and a plurality of groups of secondary sensor devices coupled to the primary sensor device. The primary sensor device receives a master clock signal from the control device and outputs, to each group of secondary sensor devices, a respective secondary clock signal with a frequency lower than the primary clock signal. The primary sensor device generates primary sensor data. The primary sensor device receives secondary sensor data from each group of secondary sensor devices. The primary sensor device combines the primary sensor data and all of the secondary sensor data into a sensor data stream with a time division-multiplexing scheme and outputs the sensor data stream to the control circuit.