The invention provides a method for synchronizing timing clocks in wireless communication, e.g. DECT based, between a timing master (P_l) and a timing slave (P_f). The timing master measures (MPD1) a phase offset between its internal clock and a reference clock, e.g. a network clock, e.g. IEEE 1588 over an Ethernet connection. Next, the timing master transmits (TPD1) data indicative of said measured phase offset to the timing slave or timing slaves, which also measure their phase offset between their internal clocks and the reference clock. Next, the timing slave(s) adjust (APD2) their phase offset between their respective internal clocks and the reference clock in response to the received data indicative of measured phase offset from the timing master. Thus, the timing slaves can ensure that they provides the same phase offset between their internal clocks and the reference clock as the timing master. Thus, DECT synchronization can be obtained in spite of a reference clock with a limited precision.

A baseline difference is determined between a slave line card time stamp corresponding to a slave line card frame sync signal and a master line card time stamp corresponding to a master line card frame sync signal. The slave line card generates subsequent slave line card time stamps for subsequent slave line card frame sync signals and the master line card generates subsequent master line card time stamps for subsequent master line card frame sync signals. Current differences are determined between subsequent slave line card time stamps and the subsequent master line card time stamps and the current differences are compared to the baseline difference. When a mismatch difference occurs (current difference differs from the baseline difference), the mismatch difference causes a phase-locked loop in the master line card to be adjusted or an offset to be provided to the master line card time of day counter.

A channel multiplexing method for reading out a detector signal is provided, including steps: grouping L detectors to form a first source signal and a second source signal; respectively introducing L detector signals into a first signal transmission line including two readout channels A and B and a second signal transmission line including two readout channels C and D, and providing a first signal delay unit and a second signal delay unit on the first signal transmission line and the second signal transmission line; and symbolizing source detectors for forming signals according to pulses of the four readout channels A, B, C and D, and obtaining final pulse information.

A holdover mode device is illustrated. When a time synchronization source is not abnormal, a digital PLL uses a time synchronization source as its input clock, and a measurement and adjustment module calculates a variation of a frequency difference between the time synchronization source and a reference clock output by an adjustable oscillator, and builds a frequency difference prediction model according to the variation of the frequency difference. When the time synchronization source is abnormal, the digital PLL uses a buffered time synchronization source as its input clock, and the measurement and adjustment module uses the frequency difference prediction model to calculate a predicted variation of the frequency difference according to buffered frequency difference values, and generates an adjustment signal for adjusting the reference clock according to the predicted variation of the frequency difference.

Multiplexing circuitry and method for driving multiplexing circuits are provided. A circuit includes a multiplexer circuit having symmetrical data input paths driven by a half-rate clock signal and a first stage multiplexing circuit configured to provide input signals to the multiplexer circuit. The first stage multiplexing circuit is driven by quadrature clocks to generate time-shifted data.

The present application provides a data phase recovery method, system, device and storage medium for burst code stream. The method includes: in case of detecting that data burst transmission occurs on a target peer device and detecting that a data pause signal is in an invalid state, increasing a data transmission bandwidth within a preset time specified in a transmission protocol, until a clock and data recovery (CDR) completes data locking; reducing the increased data transmission bandwidth after detecting that the CDR completes data locking. In the embodiment of the present application, by combining fast locking and slow tracking, the data transmission bandwidth is only increased within the preset time specified in the protocol, rather than continuously increasing the bandwidth, which will not have a significant impact on the stability of the link.

A channel multiplexing method for reading out a detector signal is provided, including steps: grouping L detectors to form a first source signal and a second source signal; respectively introducing L detector signals into a first signal transmission line including two readout channels A and B and a second signal transmission line including two readout channels C and D, and providing a first signal delay unit and a second signal delay unit on the first signal transmission line and the second signal transmission line; and symbolizing source detectors for forming signals according to pulses of the four readout channels A, B, C and D, and obtaining final pulse information.

In some embodiments, a system comprises a clock, a root node, a radio channel network, and first and second child nodes. The clock may be configured to generate a clock signal. The root node may be configured to generate a first frame including a first payload and a first overhead and generate a second frame including a second payload and a second overhead. The first and second overheads may comprise a synchronization value based on the clock signal. The radio channel network may be in communication with the root node for transmitting the first and second frames. Each first and second child nodes may be configured to perform clock recovery including frequency synchronization using the synchronization value and a respective phase-lock loop.

A baseline difference is determined between a slave line card time stamp corresponding to a slave line card frame sync signal and a master line card time stamp corresponding to a master line card frame sync signal. The slave line card generates subsequent slave line card time stamps for subsequent slave line card frame sync signals and the master line card generates subsequent master line card time stamps for subsequent master line card frame sync signals. Current differences are determined between subsequent slave line card time stamps and the subsequent master line card time stamps and the current differences are compared to the baseline difference. When a mismatch difference occurs (current difference differs from the baseline difference), the mismatch difference causes a phase-locked loop in the master line card to be adjusted or an offset to be provided to the master line card time of day counter.

A time synchronization method is provided for a time synchronization device, wherein the time synchronization device runs a plurality of precision time protocol (PTP) instances to connect to a plurality of time synchronization domains respectively. The time synchronization method includes determining whether a frequency of a local PTP clock of the time synchronization device is changed; and updating a frequency of a local clock of the time synchronization device with the frequency of the local PTP clock in response to the frequency of the local PTP clock being changed.