Apparatus and methods relating to synchronization of communication equipment are disclosed. Synchronization information received from a bonded communication link can be used to synchronize local and/or remote communication equipment, such as femtocell sites coupled to nodes in a ring network. This may involve isolating a frequency reference signal from a DSL (Digital Subscriber Line) communication link which is a constituent link of a bonded communication link, for example. In a ring network, received synchronization information could be used in synchronizing a locally connected installation of communication equipment, and passed for transmission in the ring network for synchronizing other communication equipment. Such dropping and passing of an analog frequency reference signal could be applied in networks having other topologies as well. At least some embodiments of the invention are applicable to optical links. One or more dedicated wavelengths of an optical link could be used to transfer a frequency reference signal, for example. Other functions, such as quality monitoring, quality reporting, and/or predictive traffic forwarding may be provided in some embodiments.

An integrated circuit includes a control circuit, a primary sensor device coupled to the control circuit, and a plurality of groups of secondary sensor devices coupled to the primary sensor device. The primary sensor device receives a master clock signal from the control device and outputs, to each group of secondary sensor devices, a respective secondary clock signal with a frequency lower than the primary clock signal. The primary sensor device generates primary sensor data. The primary sensor device receives secondary sensor data from each group of secondary sensor devices. The primary sensor device combines the primary sensor data and all of the secondary sensor data into a sensor data stream with a time division-multiplexing scheme and outputs the sensor data stream to the control circuit.

A method of clock synchronization between a transmitter and a receiver includes sampling a first receiver timestamp and a second receiver timestamp of the receiver at a first time and a second time respectively, sampling a first transmitter timestamp and a second transmitter timestamp of the transmitter at a third time and a fourth time respectively, sampling a first timing synchronization function (TSF) receiver timestamp and a second TSF receiver timestamp by a Wi-Fi TSF at the first time and the second time respectively, sampling a first TSF transmitter timestamp and a second TSF transmitter timestamp by the Wi-Fi TSF at the third time and the fourth time respectively, generating an initial timestamp, generating an initial TSF timestamp, generating a target phase difference, and performing a coarse tune at a receiver system clock periodically to compensate the target phase difference.

A holdover mode device is illustrated. When a time synchronization source is not abnormal, a digital PLL uses a time synchronization source as its input clock, and a measurement and adjustment module calculates a variation of a frequency difference between the time synchronization source and a reference clock output by an adjustable oscillator, and builds a frequency difference prediction model according to the variation of the frequency difference. When the time synchronization source is abnormal, the digital PLL uses a buffered time synchronization source as its input clock, and the measurement and adjustment module uses the frequency difference prediction model to calculate a predicted variation of the frequency difference according to buffered frequency difference values, and generates an adjustment signal for adjusting the reference clock according to the predicted variation of the frequency difference.

A baseline difference is determined between a slave line card time stamp corresponding to a slave line card frame sync signal and a master line card time stamp corresponding to a master line card frame sync signal. The slave line card generates subsequent slave line card time stamps for subsequent slave line card frame sync signals and the master line card generates subsequent master line card time stamps for subsequent master line card frame sync signals. Current differences are determined between subsequent slave line card time stamps and the subsequent master line card time stamps and the current differences are compared to the baseline difference. When a mismatch difference occurs (current difference differs from the baseline difference), the mismatch difference causes a phase-locked loop in the master line card to be adjusted or an offset to be provided to the master line card time of day counter.

Examples herein describe pulse generation circuitry. The pulse generation circuitry includes a first pulse generator circuit configured to generate a first pulsed output by sampling a data input using a first clock signal having first pulses and a second clock signal having second pulses that do not overlap the first pulses. The first and second clock signals are separated by a phase shift. The pulse generation circuitry also includes a second pulse generator circuit configured to generate a second pulsed output by sampling the data input using a third clock signal having third pulses and a fourth clock signal having fourth pulses that do not overlap the third pulses. The third and fourth clock signals are separated by the phase shift. A multiplexor is configured to output a third pulsed output based on the first pulsed output and the second pulsed output.

A holdover mode device is illustrated. When a time synchronization source is not abnormal, a digital PLL uses a time synchronization source as its input clock, and a measurement and adjustment module calculates a variation of a frequency difference between the time synchronization source and a reference clock output by an adjustable oscillator, and builds a frequency difference prediction model according to the variation of the frequency difference. When the time synchronization source is abnormal, the digital PLL uses a buffered time synchronization source as its input clock, and the measurement and adjustment module uses the frequency difference prediction model to calculate a predicted variation of the frequency difference according to buffered frequency difference values, and generates an adjustment signal for adjusting the reference clock according to the predicted variation of the frequency difference.

Apparatus are disclosed to syntonize timing devices. An example apparatus includes activity detection circuitry to generate a pulse output based on a first clock and a second clock, the pulse output having a periodicity of the first clock, phase error generation circuitry to determine phase error direction indicators between the pulse output and a regenerated clock, the regenerated clock having a first frequency, proportional/integral (PI) circuitry to determine correction values based on the phase error direction indicators, the correction values to cause modification of the first frequency of the regenerated clock, and precision time protocol (PTP) timer circuitry to modify a frequency of a third clock based on accumulated ones of the correction values.

A control system includes: a time master configured to periodically transmit synchronization signals for time synchronization via a network; and circuitry connected to the time master via the network, wherein the circuitry includes a local clock and is configured to: periodically determine, for every two or more receptions of the synchronization signal via the network, a communication timing so that a frequency of the communication timing is reduced from a transmission frequency of the synchronization signal; periodically perform, in accordance with the communication timing periodically determined with the reduced frequency, data exchange with the time master including transmission of a response signal to the synchronization signal; acquire an offset of the local clock with respect to the time master based on a result of the data exchange; correct the local clock in accordance with the offset; and control a machine based on the corrected local clock.

A timing adjustment method includes: reporting, by a terminal supporting an internet of things (IoT) service in a satellite communication system, target information, the target information is information related to a timing adjustment requested by the terminal; and performing, by the terminal, in response to not receiving new timing adjustment information, the timing adjustment based on original timing adjustment information; or performing, by the terminal, in response to receiving new timing adjustment information, the timing adjustment based on the new timing adjustment information.