Provided are a method for performing port configuration of a 5G system (5GS) for providing a time synchronization service, and a network entity performing the same. A method for performing port configuration may include: when a grandmaster (GM) is determined to be a Time Sensitive Networking (TSN) GM outside the 5GS, performing, by a Network Exposure Function (NEF), port configuration of the 5GS in a Best Master Clock Algorithm (BMCA) scheme; and when the GM is determined to be a 5GS GM inside the 5GS, or the TSN GM outside the 5GS that does not support the BMCA, performing, by the NEF, port configuration of the 5GS in an external port configuration scheme.

An electronic device is disclosed. The electronic device comprises a first clock configured to operate at a frequency. First circuitry of the electronic device is configured to synchronize with the first clock. Second circuitry is configured to determine a second clock based on the first clock. The second clock is configured to operate at the frequency of the first clock, and is further configured to operate with a phase shift with respect to the first clock. Third circuitry is configured to synchronize with the second clock.

A transmitting system includes an outputting apparatus and a multiplexing apparatus. The outputting apparatus transmits MMTP packets to which an NTP short format timestamp is added. The multiplexing apparatus multiplexes the MMTP packets. The multiplexing apparatus includes an extractor, a controller, a determiner, a management information generator, a continuity determiner, and a transmission timing adjuster. The transmission timing adjuster writes, for adjustment of a transmission timing of an MMTP packet being close to an MMTP packet in which an NTP short format timestamp value is discontinuous, time information taking a leap second processing into consideration, to the NTP short format timestamp of the MMTP packet.

A network TAP includes four serial transceivers on a printed circuit board. Each serial transceiver has a medium-dependent interface and a serial differential interface that includes a differential input and a differential output. A passive tap circuit arrangement is configured to be operative at up to 10 Gbps or a higher data rate and configures the differential output signal from the differential output of the first serial transceiver as two single-ended signals that are received respectively by the respective differential inputs of the second and third serial transceivers. It also configures the differential output signal from the differential output of the second serial transceiver as two single-ended signals that are received respectively by the respective differential inputs of the first and fourth serial transceivers. In one embodiment according to the present invention, the four serial transceivers are pluggable transceiver modules.

Disclosed embodiments relate, generally, to improved data reception handling at a physical layer (PHY). Some embodiments relate to end of line systems that include legacy media access control (MAC) and PHY that implement improved data reception handling disclosed herein. The improved data reception handling improves the operation of the end of line systems, and the MAC more specifically, and in some cases to comply with media access tuning protocols implemented at the physical layer.

A method and an apparatus for evaluating quality of a software running environment of a device. The method includes: determining time deviation values of a to-be-evaluated device in all of N time periods; determining an inherent deviation value based on the time deviation values in all of the N time periods; determining, based on the time deviation values in all of the N time periods and the inherent deviation value, timing jitter amplitudes in all of the N time periods; and selecting a target timing jitter amplitude with a largest timing jitter amplitude. The evaluation parameter for measuring the quality of the software running environment of the to-be-evaluated device can be obtained, and the quality of the software running environment of the device can be evaluated by using the evaluation parameter.

A method and a structure for determining a global clock among systems are disclosed. When a standardized time reference is required among systems, a reference clock source may transmit a calibration signal, and a transmitting time T.sub.d (0) may be recorded. Each system may respectively record an arrival time T.sub.a (n), transmit a return signal to a signal recording unit of the reference clock source, and record a transmitting time T.sub.b (n), after receiving the calibration signal. Similarly, because of different distances, the signal recording unit may record arrival times T.sub.d (n) of the return signals subsequently, and determine time delays Delay (n) between systems and the reference clock source respectively. When all the systems are required to have a completely standardized time reference, a corresponding Delay (n) may be acquired and transmitted to each system. Each system may determine zero deviations T.sub.c (n) of various local clocks from the reference clock source, and take T.sub.c (n) as a correction parameter to correct its own system clock, so that the local clocks of all the systems have a completely standardized time reference.

Techniques efficiently serialize multiple data streams using quadrature clocks. Serializer employs first, second, third, and fourth clock signals. Serializer receives multiple data streams via registers, with each of four paths comprising a register, buffer, and switch, with registers of first and fourth paths associated with third clock signal, and registers of second and third paths associated with first clock signal, and with switches of first and fourth paths associated with first clock signal, and switches of second and third paths associated with third clock signal. Switches of first and second paths transfer respective data bits to fifth switch via another buffer, wherein fifth switch is associated with a delayed second clock signal of a time delay component (TDC). Switches of third and fourth paths transfer respective data bits to sixth switch via another buffer, wherein sixth switch is associated with a delayed fourth clock signal of TDC.

A data transceiving system, comprising: a data receiving apparatus, comprising a data receiving side command pin and at least one data receiving side data pin; a data transmitting apparatus, comprising a data transmitting side command pin and at least one data transmitting side data pin. The data receiving apparatus transmits a first command signal from the data receiving side command pin to the data transmitting side command pin, and the data transmitting apparatus transmits a first response signal from the data transmitting side command pin to the data receiving side command pin. The data transmitting apparatus transmits data from the data transmitting side data pin to the data receiving side data pin. The data transmitting apparatus transmits a first data sampling clock signal from the data transmitting side command pin to the data receiving side command pin, to sample the data.

A timestamp unit and a communication control unit for a user station. The timestamp unit includes a memory, which cyclically stores a timestamp of a message, which is transmitted via a communication network, an address counter, which is incrementable with each storing of a timestamp of a message, so that the value of the address counter corresponds to an address at which the timestamp is stored in the memory, a first interface to a host control unit via which the timestamp of a message is capturable, and a second interface to a communication control unit, which creates or reads at least one message for/from the user station, the interface including a connection for receiving a trigger signal from the communication control unit, which prompts the capturing of a timestamp, and a connection for transmitting a signal to the communication control unit, which includes the value of the address counter.