A method for synchronous processing exchange orders, comprising: creating a first batch of orders by accumulating exchange orders received within a first time period, TP1; creating a second batch of orders by accumulating exchange orders received within a second time period, TP2; and processing the orders from the first batch within the second time period, TP2.

A cross connect apparatus or system with transparent clocking, consistent with embodiments described herein, connects a selected source or ingress port to a selected destination or egress port and clocks data out of the selected egress port using a synthesized clock that is adjusted to match a recovered clock from the selected ingress port. A transparent clocking system may generate the synthesized clock signal with adjustments in response to a parts per million (PPM) rate detected for the associated recovered clock signal provided by the selected ingress port. The cross connect system with transparent clocking may be a 400 G cross connect system with 10 G resolution. The cross connect system with transparent clocking may be used in optical transport network (OTN) applications, for example, to provide an aggregator and/or an add-drop multiplexer (ADM) or to provide a reconfigurable optical add-drop multiplexer (ROADM) upgrade to a higher data rate.

A system and method employing a precisely synchronized time in connection with a distributed hardware architecture are disclosed. Using an independent and trusted time signal and a second transition pulse signal, each resource in the distributed hardware architecture may be synchronized precisely to the same absolute time.

A technique for facilitating clock recovery in a node of a packet-based network is disclosed. The node is synchronized with other nodes based on a master-slave clock mechanism. A list of backup master clock node is maintained for the node, which includes at least one backup master clock node for the node, and in response to occurrence of a synchronization related event, a master clock node of the node is switched from the current master clock node to a backup master clock node selected from the list. A master clock node reselection message is generated and transmitted to the switched backup master clock node for the switched backup master clock node to reselect its master clock node.

Implementations of the present disclosure involve an apparatus and/or method for adjusting a counter in a computing system to account for drift of the counter value over time compared to another counter of the system. In particular, a processor of the computing system that includes a local counter component may access a counter component of another processor of the system, referred to as the reference counter. By comparing the value of the reference counter to the local counter, the processor may determine any drift that may have occurred over a period of time in the local counter. The calculated drift, or counter error, may be converted into one or more adjustments to the local counter to synchronize the local counter with the reference counter. In one embodiment, the adjustment to the local counter includes increasing the rate at which the local counter is incremented for a period of time.

A system and method employing a precisely synchronized time in connection with a distributed hardware architecture are disclosed. Using an independent and trusted time signal and a second transition pulse signal, each resource in the distributed hardware architecture may be synchronized precisely to the same absolute time.

Embodiments of a method for clock synchronization in a radio frequency identification (RFID) equipped device, an RFID equipped device, and a hand-held communications device are described. In one embodiment, a method for clock synchronization in an RFID equipped device involves measuring a difference between a field clock frequency generated from an external clock and an internal clock frequency generated from an internal clock and generating outgoing bits in the RFID equipped device in response to the measured difference. Generating the outgoing bits involves adjusting the bit length of at least one of the outgoing bits in response to the measured difference. Other embodiments are also described.

In various embodiments, a method is provided. In this method, a first signal is received from a master node, and is sampled to obtain a first sample. The first sample is then quantized to obtain a quantized form of the first sample. A first synchronization sequence is detected from the quantized form of the first sample at T2. First information is received from the master node and the first information is used to indicate a moment T1 at which the master node sends the first synchronization sequence. A second synchronization sequence is sent to the master node at T3. Second information received from the master node and the second information is used to indicate a moment T4 at which the master node detects a quantized form of the second synchronization sequence. Time synchronization is performed based on T1, T2, T3, and T4.

A method for synchronizing a first time domain with a second time domain of a system on chip includes a detection of at least one periodic trigger event generated in the first time domain, the second time domain or in a third time domain; acquisitions, made at the instants of the at least one trigger event, of the current timestamp values representative of the instantaneous states of the time domain(s) other than the trigger time domain; a comparison, made in the third time domain, between differential durations between current timestamp values which are respectively acquired successively; and a synchronization of the second time domain with the first time domain, on the basis of the comparison.

A communication system comprises a clock generator configured to generate a plurality of system clock signals used to synchronize components included in each of communication nodes in the communication system based on an external clock signal provided by an external clock source located outside the communication system and a physical layer configured to transmit any one of the generated system clock signals to a small cell communicatively connected to an end communication node of the communication system.