A subscriber of a wired data network, in particular of a local bus system, having internal clock generator for generating a clock generator signal having a clock generator frequency for the subscriber, a receive circuit for receiving a serial receive data stream, a processing circuit for inputting parallel receive data and for outputting parallel transmit data, and a transmit circuit for transmitting a serial transmit data stream. The receive circuit has a serial-to-parallel converter for converting serial receive data of the serial receive data stream into the parallel receive data. The receive circuit has a synchronization unit for synchronizing the internal clock generator to the data clock frequency contained in the serial receive data stream. The synchronization unit is configured for detecting transitions in the received serial receive data stream and for controlling the clock generator frequency of the internal clock generator as a function of the detected transitions.

A communication system (1000) includes communication devices (10, 20) to share common time after correction of synchronization error including a communication delay with each other via a network (400). The communication device (10) includes a set time acquirer to acquire set time set by a user, a setter to set the set time as first system time, which is system time of the communication device (10), and a time difference data transmitter to transmit time difference data, which indicates a time difference between the common time and the set time, to the communication device (20). The communication device (20) includes a time difference data receiver to receive the time difference data, and a setter to set the sum of the common time and the time difference indicated by the time difference data as second system time, which is system time of the communication device (20).

A reconfigurable data acquisition card including at least one field programmable gate array (FPGA) and a configurable bus switch coupled with the FPGA. The bus switch forms at least first and second ports used by the FPGA, the bus switch being adaptable for insertion into a connection having a number of lanes at least equal to a combined number of lanes in the first and second ports. The data acquisition card further includes multiple optical transmitters and optical receivers. Each optical transmitter and optical receiver is coupled with a corresponding transceiver in the FPGA via at least one optical fiber having multiple communication links. Timing circuitry in the data acquisition card is coupled with clock generation and distribution circuitry in the FPGA and is configured to distribute clock and timing signals to detector front-ends with fixed latency and to synchronize input/output links with a system clock generated by the FPGA.

Embodiments of this application provide a time synchronization method, a service board, and a network device. After clock board times between service boards are synchronized, the service board obtains a CPU time and the clock board time of the service board according to a preset periodicity, and makes a record; when performing CPU time synchronization between the service boards, the service board obtains a current CPU time of the service board, and calculates a synchronization time of the CPU based on the current CPU time, and a last recorded CPU time and clock board time; and adjusts the CPU time of the service board to the synchronization time. After the clock board times between the service boards that need to implement CPU high-precision time synchronization are synchronized by using a high-precision time synchronization protocol, the CPU time of each service board is adjusted to a corresponding synchronization time.

A communication system (1000) includes communication devices (10, 20) to share common time after correction of synchronization error including a communication delay with each other via a network (400). The communication device (10) includes a set time acquirer to acquire set time set by a user, a setter to set the set time as first system time, which is system time of the communication device (10), and a time difference data transmitter to transmit time difference data, which indicates a time difference between the common time and the set time, to the communication device (20). The communication device (20) includes a time difference data receiver to receive the time difference data, and a setter to set the sum of the common time and the time difference indicated by the time difference data as second system time, which is system time of the communication device (20).

System and techniques for synchronizing a real-time clock and a network clock are described herein. A network device maintains an always running time (ART) replica of an ART in a compute system. The network device samples network time updates (e.g., precision time protocol messages) and the ART replica to produce error correction of the ART replica to the network time. The error correction is written to memory of the compute device to enable high precision synchronization between clock sources local to the compute device and the network time.

A system can, in response to determining to capture bio telemetry data associated with client devices, synchronize respective second clock times of respective client devices with a first clock time maintained by a network time protocol server, wherein the respective client devices are configured to capture the bio telemetry data of respective users associated with the client devices, wherein the respective users are associated with respective user accounts. The system can synchronize the bio telemetry data of the respective users based the respective second clock times.

A communication system comprises a clock generator configured to generate a plurality of system clock signals used to synchronize components included in each of communication nodes in the communication system based on an external clock signal provided by an external clock source located outside the communication system and a physical layer configured to transmit any one of the generated system clock signals to a small cell communicatively connected to an end communication node of the communication system.

An optical transceiver is pluggable to any one of a first apparatus and a second apparatus and includes a clock recovery circuit capable of regenerating a clock signal from an electrical signal, a memory storing a first program including a first transmission rate and a second program including a second transmission rate, and a processor executing a program with a higher priority level in a boot process. The processor sets a transmission rate of a program being executed to a transmission rate set value, and operates the clock recovery circuit. In accordance with an interrupt request, the processor sets, based on regeneration or non-regeneration of the clock signal, the priority level of the first or second program that is being executed to be lower than the priority level of the first or second program that is not being executed, and boots up.

This application provides a communication method and an optical module. The method includes: A first optical module determines a first delay. The first optical module sends the first delay to an interface chip. According to the communication method and the optical module that are provided in this application, a delay in the optical module can be reported to the interface chip, so as to improve precision of time synchronization between a master clock and a slave clock, thereby further improving clock precision of a network device.