The invention relates to a method for providing a fault-tolerant global time via a time server in a distributed real-time computer system, wherein the time server comprises four components which are connected to one another via a bi-directional communication channel. At a priori defined periodic, internal synchronization times, each of the four components transmits an internal synchronization message, which is simultaneously transmitted to the other three components, from which each internal computer of a component determines a correction term for the tick counter contained in its component and corrects the reading of the local tick counter by this correction term.

A circuit and method enables multiple serializer/deserializer (SerDes) data lanes of a physical layer device (PHY) to operate across a broad range of diversified data rates that are independent from lane to lane. The multiple SerDes data lanes may operate at data rates independent from one another. A single low frequency clock is input to the PHY. A frequency of the single low frequency clock is increased via a common integer-N phase-locked loop (PLL) on the PHY to produce a higher frequency clock. Each of the SerDes data lanes is operated, independently, as a fractional-N PLL that employs the higher frequency clock. Use of the common integer-N PLL enables modulation noise of the fractional-N PLLs to be suppressed by moving the modulation noise to higher frequencies where a level of the modulation noise is filtered, avoiding use of high risk noise cancellation techniques.

An object of this technology is for one apparatus to effectively notify the other apparatus whether or not synchronization target clocks are correctly synchronized therebetween. A wireless apparatus includes a main control section, a wireless control section, and a clock synchronization management section. The main control section manages time using a first clock (synchronization target clock). The wireless control section manages time using a second clock (reference clock). The synchronization management section manages a clock synchronization state. The wireless control section notifies another wirelessly connected wireless apparatus of information regarding the clock synchronization state through transmission of a frame.

An adjustable high resolution timer (100) for synchronizing a local clock to an external reference clock includes frequency offset acquisition and compensation unit (110) configured to acquire a frequency offset difference between the local and external reference clock and to generate frequency adjustment signals based on the frequency offset difference; a time drift tracking and adjustment unit (120) configured to continuously monitor the local and external reference clocks for phase offset differences therebetween and to generate timing adjustment signals based on the phase offset difference; a nanosecond timer core unit (140) configured to generate a frequency and phase adjusted nanosecond timer output signal in response to the frequency adjustment signals and timing adjustment signals; and a pulse generation unit (130) for generating a plurality of output pulse signals that are synchronized with the external reference clock in response to the frequency and phase adjusted nanosecond timer output signal.

A circuit and method enables multiple serializer/deserializer (SerDes) data lanes of a physical layer device (PHY) to operate across a broad range of diversified data rates that are independent from lane to lane. The multiple SerDes data lanes may operate at data rates independent from one another. A single low frequency clock is input to the PHY. A frequency of the single low frequency clock is increased via a common integer-N phase-locked loop (PLL) on the PHY to produce a higher frequency clock. Each of the SerDes data lanes is operated, independently, as a fractional-N PLL that employs the higher frequency clock. Use of the common integer-N PLL enables modulation noise of the fractional-N PLLs to be suppressed by moving the modulation noise to higher frequencies where a level of the modulation noise is filtered, avoiding use of high risk noise cancellation techniques.

An electronic device comprises a first circuit portion comprising one or more components, including a first counter, which are clocked by a first clock signal. The first circuit portion is arranged to receive a data stream comprising a plurality of data signals. A second circuit portion comprises one or more components clocked by a second clock signal and a second counter not clocked by the second clock signal. The first clock signal is not synchronised to the second clock signal. The second circuit portion is arranged to: receive samples of the data stream from the first circuit portion at a sample rate and to time-stamp each received sample with a count value of the second counter. The second circuit portion increments the count value of the second counter by a predetermined increment value for each received sample.

A subscriber of a wired data network, in particular of a local bus system, having internal clock generator for generating a clock generator signal having a clock generator frequency for the subscriber, a receive circuit for receiving a serial receive data stream, a processing circuit for inputting parallel receive data and for outputting parallel transmit data, and a transmit circuit for transmitting a serial transmit data stream. The receive circuit has a serial-to-parallel converter for converting serial receive data of the serial receive data stream into the parallel receive data. The receive circuit has a synchronization unit for synchronizing the internal clock generator to the data clock frequency contained in the serial receive data stream. The synchronization unit is configured for detecting transitions in the received serial receive data stream and for controlling the clock generator frequency of the internal clock generator as a function of the detected transitions.

A radio receiver device, arranged to receive a radio signal modulated with a plurality of data symbols, comprises an analogue-to-digital converter that is clocked by a first clock signal and is arranged to receive the radio signal and produce a digital signal. A digital circuit portion, arranged to receive the digital signal produced by the analogue-to-digital converter, comprises digital processing units that are clocked by a second clock derived from the first clock and arranged to process the digital signal and produce an output signal at an output sample rate. A counter, clocked by the second clock, counts a number of samples at the output sample rate. A network timer clocked by a reference of a network clock produces a receiver enable flag which is synchronised to the first clock. The counter is enabled only when the synchronised flag is set. The counter is arranged to set a trigger flag when the number of samples exceeds a predetermined threshold. A buffer is arranged to receive the output signal and is enabled only when the trigger flag is set.

A SerDes system is provided. The SerDes system includes channel circuits, a PLL circuit, first and second buffers, and first and second capacitors. Each channel circuit is coupled to the first and second clock lines. The PLL circuit generates a first differential signal including first and second clock signals. The first buffer buffers the first clock signal. The second buffer and buffers the second clock signal. The first capacitor receives the buffered first clock signal and outputs a third clock signal to the first clock line. The second capacitor receives a buffered second clock signal and outputs a fourth clock signal to the second clock line. A swing of a second differential signal comprising the third clock signal and the fourth clock signal is smaller than a swing of the first differential signal.

A method for synchronizing radio frequency carrier correction of dynamic radio frequency carriers is provided. The method includes receiving a carrier configuration from a carrier controller to modulate a carrier signal based on the carrier configuration and receiving a time reference and timestamped carrier configuration information from the carrier controller. The timestamped carrier configuration information includes a correlation between a plurality of timestamps and a plurality of carrier attributes. The method also includes synchronizing an internal clock of a RF correction preprocessor to the time reference, and receiving a modulated carrier signal from the RF modem. The method further includes generating a radio frequency correction set including a correction solution for each of a plurality of timeslots based on the timestamped carrier configuration information, and generating a corrected carrier signal based on applying the RF correction set to the modulated carrier signal at a coincident timeslot.