A turbo decoder circuit performs a turbo decoding process to recover a frame of data symbols from a received signal comprising soft decision values for each data symbol of the frame. The data symbols of the frame have been encoded with a turbo encoder comprising upper and lower convolutional encoders which can each be represented by a trellis, and an interleaver which interleaves the encoded data between the upper and lower convolutional encoders. The turbo decoder circuit comprises a clock, a configurable network circuitry for interleaving soft decision values, an upper decoder and a lower decoder. Each of the upper and lower decoders include processing elements, which are configured, during a series of consecutive clock cycles, iteratively to receive, from the configurable network circuitry, a priori soft decision values pertaining to data symbols associated with a window of an integer number of consecutive trellis stages representing possible paths between states of the upper or lower convolutional encoder. The processing elements perform parallel calculations associated with the window using the a priori soft decision values in order to generate corresponding extrinsic soft decision values pertaining to the data symbols. The configurable network circuitry includes network controller circuitry which controls a configuration of the configurable network circuitry iteratively, during the consecutive clock cycles, to provide the a priori soft decision values for the upper decoder by interleaving the extrinsic soft decision values provided by the lower decoder, and to provide the a priori soft decision values for the lower decoder by interleaving the extrinsic soft decision values provided by the upper decoder. The interleaving performed by the configurable network circuitry controlled by the network controller is in accordance with a predetermined schedule, which provides the a priori soft decision values at different cycles of the one or more consecutive clock cycles to avoid contention between different a priori soft decision values being provided to the same processing element of the upper or the lower decoder during the same clock cycle. Accordingly the processing elements can have a window size which includes a number of stages of the trellis so that the decoder can be configured with an arbitrary number of processing elements, making the decoder circuit an arbitrarily parallel turbo decoder.

An error correction system includes M decoding units, each configured to perform decoding on the X first operation codes and the Y second operation codes; the decoding unit includes: a decoder, configured to receive the X first operation codes and output N first decoded signals, each corresponding to a respective one bit of the N data; a first AND gate unit, configured to receive and perform a logical AND operation on Z selected operation codes; an NOR gate unit, configured to receive and perform a logical NOR operation on (Y−Z) unselected operation codes; and N second AND gate units, each having an input terminal connected to an output terminal of the first AND gate unit, an output terminal of the NOR gate unit and one of the first decoded signals.

A method for decoding data by an electronic device is provided. The method includes receiving, by the electronic device, encoded data, determining, by the electronic device, a sparsity of a plurality of Machine Learning (ML) models of a turbo decoder of the electronic device for decoding the encoded data based on Quality-of-Service (QoS) parameters, and decoding, by the electronic device, the encoded data using the turbo decoder based on the determined sparsity.

A packet processing technique can include receiving a packet, and parsing the packet based on a protocol field to generate a parse result vector. The parse result vector is used to select between forwarding the packet to a virtual machine executing on a host processing integrated circuit, forwarding the packet to a physical media access controller, multicasting the packet to multiple virtual machines executing on the host processing integrated circuit, and sending the packet to a hypervisor.

According to certain embodiments, a method performed by a network node comprises transmitting a transmission of system information. The transmission comprises coded bins obtained by reading from a circular buffer. The transmission is transmitted in a first set of subframes corresponding to subframes #4 of a plurality of radio frames. The method further comprises transmitting an additional transmission of the system information. The additional transmission comprises additional coded bits obtained by continuing reading from the circular buffer. The additional transmission is transmitted in a second set of subframes corresponding to subframes of the plurality of radio frames other than subframes #4.

Methods, systems, and devices for wireless communications are described. A transmitting device may allocate a set of information bits into multiple subsets of bits corresponding to channel instances of a channel. The transmitting device may encode a first subset of bits according to a first channel coding scheme for a first channel instance and a second subset of bits according to a second channel coding scheme for a second channel instance. The transmitting device may input encoded subsets of bits to a polarizing transform, which may output a set of encoded polarized bits that are transmitted to a receiving device. Upon reception of the encoded polarized bits, the receiving device may apply a depolarizing transform to obtain multiple subsets of bits corresponding to channel instances of the channel, and may decode each subset of bits according to a respective channel coding scheme.

A packet processing technique can include selecting a protocol field from the packet, and performing a comparison of the selected protocol field with comparison data in a compare logic array to output a protocol index. The protocol index can be used as an address to read parsing commands from a parse control table, and a parse result can be generated based on executing the parsing commands on the packet. The parse results are used to derive a parse result vector, which can be used by a forwarding engine to forward the packet.

Systems and methods are disclosed for providing H-ARQ transmissions in respect of a set of horizontal code blocks are combined in a code. Retransmissions contain vertical parity check blocks which are determined from verticals from the set of horizontal code blocks. Once all the vertical parity check blocks have been transmitted, a new set may be determined after performing interleaving upon either the content of the horizontal code blocks, in the case of non-systematic horizontal code blocks, or over the content of encoder input bits in the place of systematic horizontal code blocks. The interleaving may be bitwise or bit subset-wise. The retransmissions do not contain any of the original bits. In the decoder, soft decisions are produced, and nothing needs to be discarded; decoding will typically improve with each retransmission.

An error correction system includes M decoding units, each configured to perform decoding on the X first operation codes and the Y second operation codes; the decoding unit includes: a decoder, configured to receive the X first operation codes and output N first decoded signals, each corresponding to a respective one bit of the N data; a first AND gate unit, configured to receive and perform a logical AND operation on Z selected operation codes; an NOR gate unit, configured to receive and perform a logical NOR operation on (Y−Z) unselected operation codes; and N second AND gate units, each having an input terminal connected to an output terminal of the first AND gate unit, an output terminal of the NOR gate unit and one of the first decoded signals.

Systems and methods for more efficiently decoding generalized product codes (GPC) are described. A receiving device equipped with a decoder is configured to receive GPC-encoded signals and implement an early termination method to avoid executing multiple operations of the decoding scheme typically used by the receiving device. The receiving device can identify whether a particular condition is satisfied when decoding a signal, and if the condition is satisfied, can omit certain operations of the decoding scheme and thereby reduce power consumption. The particular condition can be satisfied when the syndromes for sign bits in a codeword associated with the received signal are zero.