A master of a bus system for process control with one slave and a bus. A transceiver circuit transmits and receives for process control by data packets. A channel has a receive memory area. The transceiver circuit is set up to write the receive data of a data packet received via the bus into the receive memory area. The channel has at least one selection circuit, an output of the selection circuit being connected to the transceiver circuit. The selection circuit has a first input for selecting initial data. The selection circuit has a second input, the second input being connected to the receive memory area, and the selection circuit is configured to select the transmit data from the initial data and/or the data written into the receive memory area and to output the transmitted data to the transceiver circuit for a data packet to be transmitted.

A communication system includes a master device and a plurality of slave devices. Each slave device stores a synchronization period and a correction amount of a difference between a time of the master device and a time of the slave device. The master device acquires the correction amount from the slave device, calculates a correspondence relationship between a synchronization period and the correction amount based on the correction amount, calculates a target synchronization period in the slave device based on the correspondence relationship, classifies each slave device into a plurality of groups based on the target synchronization period in each slave device, and sets a maximum target synchronization period among the target synchronization periods of at least one slave device classified into each group to a new synchronization period in which the master device performs the time synchronization along with the at least one slave device.

A communicating entities include one master entity, configured for communicating according to a first protocol at least, and a plurality of slave entities. The slave entities include a first group of slave entities able to support communications according to said first protocol and unable to support communications according to a second protocol, and a second group of slave entities able to support communications according to at least said second protocol. The first protocol is implemented by a token passing with communication data from the master entity to successively each neighbour slave entity, until the token reaches again the master entity, defining thus a first cycle according to the first protocol. The second protocol is implemented by passing a data frame including data intended to entities of said second group, one current entity of said second group, when receiving said data frame.

In an in-vehicle network, a master device and a plurality of slave devices communicate with each other. A plurality of semiconductor relays for supplying power to the corresponding slave devices is provided for each of the plurality of slave devices in the master device. IDs corresponding to the plurality of semiconductor relays are stored in a flash ROM of the master device. The master device transmits the corresponding ID each time the semiconductor relays are turned on by sequentially turning on the semiconductor relays. The plurality of slave devices set the ID received after power supply as its own ID.

A communication system includes a master node and a slave node connected to the master node via a bus. The master node transmits a header including identification information assigned to a designated function in accordance with a schedule preset individually for the designated function. The slave node has a plurality of functions for each of which a response different from each other is transmitted. The slave node returns the response related to the designated function upon receipt of the header when the designated function assigned with the identification information included in the header is one of the plurality of functions of the slave node.

Embodiments of a system for improving automobile safety are disclosed.

An example programmable integrated circuit (IC) includes a processor, a plurality of endpoint circuits, a network-on-chip (NoC) having NoC master units (NMUs), NoC slave units (NSUs), NoC programmable switches (NPSs), a plurality of registers, and a NoC programming interface (NPI). The processor is coupled to the NPI and is configured to program the NPSs by loading an image to the registers through the NPI for providing physical channels between NMUs to the NSUs and providing data paths between the plurality of endpoint circuits.

A vehicle seat with a ventilation device which is paired with at least two fans. It is provided that only one of the at least two fans is provided with a bus signal as an input signal which is converted into a PWM signal for the at least one other fan in a signal converter wherein the signal converter has at least one output which provides the PWM signal, generated for the at least one fan, to an input of the at least one further fan.

A method and a data bus subscriber are described for processing process data in a local bus, in particular a ring bus, the method including receiving a first symbol during a first number of working cycles, with the first symbol comprising first process data; loading at least one first instruction from an instruction list during the first number of working cycles, receiving a second symbol during a second number of working cycles, with the second symbol comprising second process data, processing the first process data contained in the first symbol with the at least one loaded first instruction during the second number of working cycles, and loading at least one second instruction for processing the second process data of the second symbol during the second number of working cycles.

Provided is a control device that includes: a communication unit; one or more functional units; and a communication line connecting the communication unit and the one or the plurality of functional units. The communication unit includes: a computation processing unit in which a processor executes one or more tasks; a communication circuit which handles the transmission and reception of communication frames via the communication line; and a control circuit connected to the computation processing unit and the communication circuit. The control circuit includes: a first Direct Memory Access (DMA) core for accessing the computation processing unit; a second DMA core for accessing the communication circuit; and a controller which, in response to a trigger from the computation processing part, provides sequential commands to the first DMA core and the second DMA core in accordance with a predefined descriptor table.