The invention relates to a reception device, etc., applied to a transmission/reception system capable of performing high-speed transmission, having a structure to enable to adjust an offset without increasing a circuit area and power consumption. The reception device includes a signal input unit including an offset adjusting circuit, and an adjustment unit. When a pair of adjusting signals of which a voltage between signals is fixed to zero V is outputted from a transmission device to the reception device connected to each other via a differential signal line including at least a pair of signal lines, the signal input unit that has received the pair of adjusting signals outputs logical value data corresponding to the voltage between signals. The adjustment unit determines adjustment value data to adjust the offset of a threshold to obtain the logical value data based on the logical value data inputted in a certain period.

Some embodiments include apparatus and methods using an input unit including a first transistor to receive a first signal of a differential signal pair, a second transistor to receive a second signal of the differential signal pair, and a third transistor to receive a clock signal, with the third transistor coupled to the first and second transistors at a node. The input unit includes a circuit component to form a first circuit path between the node and a supply node during a first phase of the clock signal. The third transistor is to form a second circuit path between the node and the supply node during a second phase of the clock signal. The apparatus includes an output unit coupled to the first and second transistors to generate output information based on voltages of the first and second signals during the second phase of the clock signal.

In a detection circuit, inputs correspond to received indications of vector signaling code words received by a first integrated circuit from a second integrated circuit. With four inputs, the circuit compares a first pair to obtain a first difference result and compares a second pair, disjoint from the first pair, to obtain a second difference result. The first and second difference results are then summed to form an output function. A system might use a plurality of such detection circuits to arrive at an input word. The circuit can include amplification, equalization, and input selection with efficient code word detection. The vector signaling code can be a Hadamard matrix code encoding for three input bits. The circuit might also have frequency-dependent gain, a selection function that directs one of the summation function result or the first difference result to the output function, variable gain, and/or a slicer.

A termination circuit can include an impedance component. A first port can be configured to be connected to a first node. The first node can be a node of a conductor of a cable. A first end of the cable can be configured to be connected to a signal producing circuit. A second end of the cable can be configured to be connected to a first end of a trace disposed on a substrate of a display device. A second end of the trace can be connected to a display driver integrated circuit (DDIC). The DDIC can lack a termination impedance component internal to the DDIC to provide a line termination function for a serial interface with the signal producing circuit. A second port can be configured to be connected to a second node. The impedance component can be connected between the first port and the second port.

Described herein are a method and an apparatus for minimizing within-die variations in performance parameters of a processor. The apparatus comprising: a reference generator to generate an adjustable compensated reference signal; a bias generator to generate a bias signal based on the adjustable compensated reference signal; a transmitter coupled with the bias generator to transmit an output signal; and a feedback mechanism to sample the output signal from the transmitter and to provide the sampled output signal to the bias generator.

An RF device includes an impedance transformation circuit having a plurality of first RF couplers. Each first RF coupler includes a first portion of a first transmission line winding disposed on at least one first printed circuit board (PCB) and is configured to be electromagnetically coupled to a first portion of a second transmission line winding disposed on at least one second printed circuit board (PCB). The RF device also includes a balun circuit includes a plurality of second RF couplers coupled to balanced port connections, each second RF coupler including a second portion of the first transmission line winding wound around the first portion of a first transmission line winding and configured to be electromagnetically coupled to a second portion of the second transmission line winding wound around the first portion of a second transmission line winding.

A data transmission and reception system may include: a data transmission apparatus configured to generate N Tx signals having discrete levels using N binary data, and output the N Tx signals to N single-ended signal lines, respectively, where N is a natural number equal to or larger than 2; and a data reception apparatus configured to receive the N Tx signals transmitted in parallel through the single-ended signal lines, and restore the N binary data by comparing the received N Tx signals to each other.

A termination circuit can include an impedance component. A first port can be configured to be connected to a first node. The first node can be a node of a conductor of a cable. A first end of the cable can be configured to be connected to a signal producing circuit. A second end of the cable can be configured to be connected to a first end of a trace disposed on a substrate of a display device. A second end of the trace can be connected to a display driver integrated circuit (DDIC). The DDIC can lack a termination impedance component internal to the DDIC to provide a line termination function for a serial interface with the signal producing circuit. A second port can be configured to be connected to a second node. The impedance component can be connected between the first port and the second port.

An RF device includes an impedance transformation circuit having a plurality of first RF couplers. Each first RF coupler includes a first portion of a first transmission line winding disposed on at least one first printed circuit board (PCB) and is configured to be electromagnetically coupled to a first portion of a second transmission line winding disposed on at least one second printed circuit board (PCB). The RF device also includes a balun circuit includes a plurality of second RF couplers coupled to balanced port connections, each second RF coupler including a second portion of the first transmission line winding wound around the first portion of a first transmission line winding and configured to be electromagnetically coupled to a second portion of the second transmission line winding wound around the first portion of a second transmission line winding.

In a detection circuit, inputs correspond to received indications of vector signaling code words received by a first integrated circuit from a second integrated circuit. With four inputs, the circuit compares a first pair to obtain a first difference result and compares a second pair, disjoint from the first pair, to obtain a second difference result. The first and second difference results are then summed to form an output function. A system might use a plurality of such detection circuits to arrive at an input word. The circuit can include amplification, equalization, and input selection with efficient code word detection. The vector signaling code can be a Hadamard matrix code encoding for three input bits. The circuit might also have frequency-dependent gain, a selection function that directs one of the summation function result or the first difference result to the output function, variable gain, and/or a slicer.