A coupling module can be used to communicate high speed signals between an optical transceiver and a processing module of an optical communication device, such as an optical line termination (OLT) or an optical network unit (ONU). The coupling module can adjust the common mode voltage level of a differential signal output by the optical transceiver to the common mode voltage level required by the processing module. In addition, the coupling module splits each of the differential output signals from the optical transceiver and passes the split signals to both a high-pass filter and a low-pass filter that are connected in parallel. An adapter module can be connected to the coupling module such that the coupling module can receive different differential signals from different optical transceivers.

A receiver including a first differential sense amplifier configured to amplify an input differential data signal to generate an output differential data signal; a first set of one or more differential decision feedback equalizer (DFE) taps configured to modify the output differential data signal based on a set of one or more differential tap signals, wherein the first set of one or more differential DFE taps affect an output common mode voltage associated with the output differential data signal; and a compensation circuit configured to adjusts the output common mode voltage to compensate for the effect on the output common mode voltage by the set of one or more differential DFE taps. The compensation circuit includes reference and replica receivers to generate reference and replica output common mode voltages, and a feedback circuit to adjust the output common mode voltage based on the reference and replica output common mode voltages.

A digital-to-analog conversion circuit includes a first digital-to-analog converter (DAC) and a second DAC. The first DAC includes a first current generation circuit (CGC) and a first current-to-voltage converter. The first CGC generates a first current based on a first digital code received through a first terminal to provide the first current to an output node. The second DAC includes a second CGC and a second current-to-voltage converter. The second CGC generates a second current based on a second digital code received through a second input terminal to provide the second current to the output node. The first current-to-voltage converter and the second current-to-voltage converter convert a sum of the first current and the second current to a an analog voltage corresponding to a sum of the first digital code and the second digital code, and output the analog voltage at the output node.

An analog front-end receiver including a termination resistor configured to receive first and second differential signals from different data lines, the second differential signal being differential with respect to the first differential signal, an active equalizer configured to receive a first input differential signal through a first input node and a second input differential signal through a second input node, the first and second input differential signals both having an input common mode voltage, the first and second input differential signals being based on the first and second differential signal, respectively, and output first and output differential signals to first and second output nodes, respectfully, the second output differential signal being differential with respect to the first output differential signal, and an input common mode voltage generator configured to adjust the input common mode voltage to be equal to an output common mode voltage of the first output differential signal.

A high speed but power-efficient electronic communications protocol may comprise dual simplex links, each operating in a differential high-speed mode and each capable of a low-speed signaling mode. When both links operate in high speed mode, signaling is performed in-band, with signals embedded as metadata attached to transmitted packets. When one of the links is put into a low-power mode, the return-path signaling may be performed on the two wires previously used for high-speed transmissions. One wire may be used for flow control or other signaling, while the other wire may be used for a wake command, which may initiate the low-power mode to be elevated to a high-speed mode. Multiple lanes may be organized to operate in parallel for each link, allowing for a very high speed communications protocol that may be easily switched into and out of a low-power state without additional sideband wiring.

This disclosure describes an embodiment of an invention that is sending an information and/or control data signal on a differential signal pair. This embodiment of the apparatus 200 includes an information and/or control data signal 220; a balanced differential signal pair of conductors 212 that includes a positive 202 and a negative 204 differential conductor; a first network of circuits 214 that transforms the information signal 220 into a common mode voltage on the individual conductors 202 and 204 of the balanced differential signal pair of conductors; and a second network of circuits 216 that transforms the common mode voltage on the individual conductors 202 and 204 of the balanced differential signal pair of conductors 212 back to the data signal 222; where the first network of circuits 214 couples to the second network of circuits 216 via the balanced differential signal pair of conductors 202 and 204.

A digital differential line receiver includes a differential signal to single-ended conversion amplifier coupled to receive a data line and data-complement line of a differential signal; a first termination resistor coupled to the data line of the differential signal; a second termination resistor coupled to the data-complement line of the differential signal; a first impedance-adjusting transistor coupled between the first termination resistor and a common mode line; a second impedance-adjusting transistor coupled between the second termination resistor and the common mode line; a control-voltage generator coupled to sense the common mode line and provide a control voltage, the control voltage generator configured to adjust the control voltage to a voltage level such that a combined impedance of the first termination resistor, the first impedance-adjusting transistor, the second termination resistor, and the second impedance-adjusting transistor matches a specified impedance.

An efficient communications apparatus is described for a vector signaling code to transport data and optionally a clocking signal between integrated circuit devices. Methods of designing such apparatus and their associated codes based on a new metric herein called the “ISI Ratio” are described which permit higher communications speed, lower system power consumption, and reduced implementation complexity.

Differential-signal receivers. One example is a method of operating a differential-signal receiver, the method comprising: receiving a first differential signal on a differential-signal pair, the first differential signal accompanying a common-mode voltage that is positive relative to a reference voltage of the differential-signal receiver; clamping, when the first differential signal is positive, an OUT+ node at a first voltage; and clamping, when the first differential signal is negative, the OUT- node at a second voltage.

Differential-signal receivers. One example is a method of operating a differential-signal receiver, the method comprising: receiving a first differential signal on a differential-signal pair, the first differential signal accompanying a common-mode voltage that is positive relative to a reference voltage of the differential-signal receiver; clamping, when the first differential signal is positive, an OUT+ node at a first voltage; and clamping, when the first differential signal is negative, the OUT− node at a second voltage.