A single ended receiver includes a current mode logic circuit, a differential to single amplifier, and a voltage detector. The current mode logic circuit is configured to receive an input signal and a reference voltage value and is configured to output a first output signal. The differential to single amplifier is coupled to the current mode logic circuit and is configured to receive the first output signal and to output a second output signal. The voltage detector is coupled to the differential to single amplifier and is configured to output a control signal to the differential to single amplifier according to the reference voltage value. The differential to single amplifier is further configured to adjust a voltage value of the differential to single amplifier internal signal according to the control signal, so that a duty cycle of the second output signal is adjusted.

An integrated-circuit output driver generates, in response to an input signal constrained to a first voltage range, a control signal at one of two voltage levels according to a data bit conveyed in the input signal, the two voltages levels defining upper and lower levels of a second voltage range substantially larger than the first voltage range. The output driver generates an output-drive signal constrained to a third voltage range according to the one of the two voltage levels of the control signal, the third voltage range being substantially smaller than the second voltage range.

A bias structure includes a reference voltage node connected to gate structures of a first NMOS transistor and a second NMOS transistor, a bias voltage node comprising a bias voltage, and a first op amp having a first input connected to the reference voltage, a second input connected to a drain of the first NMOS transistor, and an output connected to gate structures of a first PMOS transistor and a second PMOS transistor. The bias structure further includes a second op amp having a first input connected to the reference voltage, a second input connected to a drain of the second NMOS transistor, and an output connected to a gate structure of a third NMOS transistor and the bias voltage node. The first NMOS transistor matches a transistor of a differential pair of an integrated circuit device.

Implementations provide a receiver circuit that includes: an alternate current (AC)-coupling network to filter an input signal, the AC-coupling network including a first RC filter connected between a first input node and a first common node and a second RC filter connected between a second input node and the first common node; a differential amplifier coupled to the AC-coupling network and configured to receive a filtered input signal from the AC-coupling network and generate an output signal, the differential amplifier including a differential pair of transistors and a common-mode measurement network coupled to source terminals of a first and a second transistors in the differential pair; and a first operational amplifier having an input coupled to output terminal of the common-mode measurement network and an output coupled to the first common node.

An Alternating Current (AC) and Direct Current (DC) coupled electronic receiver system including a receiver, an AC-coupling capacitor between an input of the receiver system and the receiver, a bypass switch configured to selectively bypass the AC-coupling capacitor to DC-couple the input to the receiver, a bypass switch driving circuit configured to cause the bypass switch to switch ON and thereby DC-couple the input to the receiver, and cause the bypass switch to switch OFF and thereby AC-couple the input to the receiver, and a voltage-following transistor between a source and a gate of the bypass switch configured to maintain an OFF state of the bypass switch while the input is AC-coupled.

Implementations provide a receiver circuit that includes: an alternate current (AC)-coupling network to filter an input signal, the AC-coupling network including a first RC filter connected between a first input node and a first common node and a second RC filter connected between a second input node and the first common node; a differential amplifier coupled to the AC-coupling network and configured to receive a filtered input signal from the AC-coupling network and generate an output signal, the differential amplifier including a differential pair of transistors and a common-mode measurement network coupled to source terminals of a first and a second transistors in the differential pair; and a first operational amplifier having an input coupled to output terminal of the common-mode measurement network and an output coupled to the first common node.

An Alternating Current (AC) and Direct Current (DC) coupled electronic receiver system including a receiver, an AC-coupling capacitor between an input of the receiver system and the receiver, a bypass switch configured to selectively bypass the AC-coupling capacitor to DC-couple the input to the receiver, a bypass switch driving circuit configured to cause the bypass switch to switch ON and thereby DC-couple the input to the receiver, and cause the bypass switch to switch OFF and thereby AC-couple the input to the receiver, and a voltage-following transistor between a source and a gate of the bypass switch configured to maintain an OFF state of the bypass switch while the input is AC-coupled.

An integrated-circuit output driver generates, in response to an input signal constrained to a first voltage range, a control signal at one of two voltage levels according to a data bit conveyed in the input signal, the two voltages levels defining upper and lower levels of a second voltage range substantially larger than the first voltage range. The output driver generates an output-drive signal constrained to a third voltage range according to the one of the two voltage levels of the control signal, the third voltage range being substantially smaller than the second voltage range.

A semiconductor circuitry includes a first circuitry having a differential transistor pair and a pair of current sources connected in series to the differential transistor pair, a pair of transmission lines connected to the differential transistor pair at the opposite side to the current sources, and a second circuitry, connected to a node between the differential transistor pair and the current sources, and configured to test operations of at least the differential transistor pair and a latter-stage circuity connected to the transmission lines, in the state where the current outputs of the pair of current sources are stopped.

A first receiver receives second serial data transmitted from a second circuit. A second receiver receives first serial data transmitted from a first circuit. An automatic adjustment circuit generates a control signal so as to reduce an error rate of the first serial data received by the second receiver. A second driver drives a differential transmission path according to the second serial data including the control signal. An operation parameter of a first driver is set based on the control signal included in the second serial data.