A signal detector includes an input to receive a differential signal, a generator to generate a first voltage based on the differential signal and a second voltage based on the first voltage and a predetermined voltage, and an output stage to output a detection signal based on the first voltage and the second voltage. The differential signal includes a first signal and a second signal. The detection signal has a first value when a difference between the first and second signals is in a first range and a second value when the difference between the first and second signals is in a second range. The detection signal may indicate the presence or absence of low frequency periodic signaling for the differential signal. Such a detector may demonstrate fast response and operate at low-current.

In a detection circuit, inputs correspond to received indications of vector signaling code words received by a first integrated circuit from a second integrated circuit. With four inputs, the circuit compares a first pair to obtain a first difference result and compares a second pair, disjoint from the first pair, to obtain a second difference result. The first and second difference results are then summed to form an output function. A system might use a plurality of such detection circuits to arrive at an input word. The circuit can include amplification, equalization, and input selection with efficient code word detection. The vector signaling code can be a Hadamard matrix code encoding for three input bits. The circuit might also have frequency-dependent gain, a selection function that directs one of the summation function result or the first difference result to the output function, variable gain, and/or a slicer.

A first receiver receives second serial data transmitted from a second circuit. A second receiver receives first serial data transmitted from a first circuit. An automatic adjustment circuit generates a control signal so as to reduce an error rate of the first serial data received by the second receiver. A second driver drives a differential transmission path according to the second serial data including the control signal. An operation parameter of a first driver is set based on the control signal included in the second serial data.

Methods, systems, and devices for mitigating supply noise in single-ended current mode logic (CML) transmitters are described. A first current source may generate a first bias current for a first differential transistor pair included in a CML transmitter, and a second current source may generate a second bias current for a second differential transistor pair. The first differential transistor pair may route the first bias current through either leg of the first differential transistor pair based on a polarity of an input signal and the second differential transistor pair may route the second bias current through either leg of the second differential transistor pair based on the polarity of the input signal. Based on a first polarity, the second bias current may be routed to a ground reference, and based on a second polarity, the second bias current may be routed through the first differential transistor pair to modify a load current internal to the CML transmitter.

A technique for attenuating common mode transient events uses a differential receiver circuit including a band-stop filter having a stopband f.sub.SB around a notch frequency f.sub.n of a received signal. The differential receiver circuit includes a first high-pass filter coupled in series with the band-stop filter. The notch frequency f.sub.n is less than a carrier frequency f.sub.c of a signal received by the differential receiver circuit. The band-stop filter may include a buffer circuit and a notch filter coupled in series with the buffer circuit. The notch filter may have a second stopband around the notch frequency f.sub.n. The differential receiver circuit may have a propagation delay that is independent of a pulse width of common mode transient energy attenuated by the differential receiver circuit.

A buffer circuit may include an input unit coupled among first and second output nodes and a common node. The input unit may be configured to change voltage levels of first and second output nodes based on an input signal. The buffer circuit may generate an output signal swinging between a voltage and a first voltage in a first operation mode, and may generate an output signal swinging between the voltage and a second voltage having a different level from the first voltage in a second operation mode.

A buffer circuit may include an input unit coupled among first and second output nodes and a common node. The input unit may be configured to change voltage levels of first and second output nodes based on an input signal. The buffer circuit may generate an output signal swinging between a voltage and a first voltage in a first operation mode, and may generate an output signal swinging between the voltage and a second voltage having a different level from the first voltage in a second operation mode.

Methods, systems, and devices for mitigating supply noise in single-ended current mode logic (CML) transmitters are described. A first current source may generate a first bias current for a first differential transistor pair included in a CML transmitter, and a second current source may generate a second bias current for a second differential transistor pair. The first differential transistor pair may route the first bias current through either leg of the first differential transistor pair based on a polarity of an input signal and the second differential transistor pair may route the second bias current through either leg of the second differential transistor pair based on the polarity of the input signal. Based on a first polarity, the second bias current may be routed to a ground reference, and based on a second polarity, the second bias current may be routed through the first differential transistor pair to modify a load current internal to the CML transmitter.

In a detection circuit, inputs correspond to received indications of vector signaling code words received by a first integrated circuit from a second integrated circuit. With four inputs, the circuit compares a first pair to obtain a first difference result and compares a second pair, disjoint from the first pair, to obtain a second difference result. The first and second difference results are then summed to form an output function. A system might use a plurality of such detection circuits to arrive at an input word. The circuit can include amplification, equalization, and input selection with efficient code word detection. The vector signaling code can be a Hadamard matrix code encoding for three input bits. The circuit might also have frequency-dependent gain, a selection function that directs one of the summation function result or the first difference result to the output function, variable gain, and/or a slicer.

Methods, systems, and devices for mitigating supply noise in single-ended current mode logic (CML) transmitters are described. A first current source may generate a first bias current for a first differential transistor pair included in a CML transmitter, and a second current source may generate a second bias current for a second differential transistor pair. The first differential transistor pair may route the first bias current through either leg of the first differential transistor pair based on a polarity of an input signal and the second differential transistor pair may route the second bias current through either leg of the second differential transistor pair based on the polarity of the input signal. Based on a first polarity, the second bias current may be routed to a ground reference, and based on a second polarity, the second bias current may be routed through the first differential transistor pair to modify a load current internal to the CML transmitter.