Signal detector

Abstract

A signal detector includes an input to receive a differential signal, a generator to generate a first voltage based on the differential signal and a second voltage based on the first voltage and a predetermined voltage, and an output stage to output a detection signal based on the first voltage and the second voltage. The differential signal includes a first signal and a second signal. The detection signal has a first value when a difference between the first and second signals is in a first range and a second value when the difference between the first and second signals is in a second range. The detection signal may indicate the presence or absence of low frequency periodic signaling for the differential signal. Such a detector may demonstrate fast response and operate at low-current.

Claims

1. A signal detector, comprising: a rectifier configured to generate a first current based on an input signal; a first circuit configured to generate a second current based on a first reference signal; a second circuit configured to generate a third current based on a common mode voltage of the input signal; a reference signal generator configured to generate a fourth current based on a second reference signal and a third reference signal; and a comparator configured to generate a detection signal based on the first current, the second current, the third current, and the fourth current.

2. The signal detector of claim 1, wherein the comparator is configured to compare a first voltage and a second voltage, the first voltage based on a sum of the first current and the second current and the second voltage based on a sum of the third current and a fourth current.

3. The signal detector of claim 2, wherein: the first voltage is based on a voltage of a first node that receives the first current and the second current, the second voltage is based on a voltage of a second node and a voltage of a third node, the second node voltage based on the first voltage, and the third node voltage based on the second voltage.

4. The signal detector of claim 3, further comprising: a filter coupled between the second node and the third node.

5. The signal detector of claim 1, further comprising: a self-bias circuit configured to input a tail current into one or more of the rectifier, the first circuit, the second circuit, and the reference signal generator.

6. The signal detector of claim 1, further comprising: an electrostatic discharge protection circuit coupled between the input line and the rectifier.

7. The signal detector of claim 1, further comprising: a circuit configured to generate the common mode voltage based on first and second signals, wherein the input signal is a differential signal that includes the first and second signals, and wherein the circuit configured to generate the common mode voltage performs electrostatic discharge protection.

8. The signal detector of claim 1, wherein: the input signal includes a first differential signal and a second differential signal, and the rectifier is configured to generate the first current based on the first differential signal and the second differential signal.

9. The signal detector of claim 1, wherein: the first reference signal corresponds to a common mode reference voltage; the second reference signal corresponds to a first reference voltage; the third reference signal corresponds to a second reference voltage; and the common mode reference voltage is between the first reference voltage and the second reference voltage.

10. The signal detector of claim 1, wherein the detection signal indicates presence of low frequency periodic signaling on a channel of an interface.

11. A signal detector, comprising: an input configured to receive a differential signal; a generator configured to generate a first voltage based on the differential signal and a second voltage based on the first voltage and a predetermined voltage; and an output stage configured to output a detection signal based on the first voltage and the second voltage, wherein the differential signal includes a first signal and a second signal and wherein the detection signal has a first value when a difference between the first and second signals is in a first range and a second value when the difference between the first and second signals is in a second range.

12. The signal detector of claim 11, wherein: the first range is a voltage less than the predetermined voltage, and the second range is a voltage greater than the predetermined voltage.

13. The signal detector of claim 11, wherein: the first value of the detection signal indicates that the differential signal does not correspond to a predetermined type of signaling, and the second value of the detection signal indicates that the differential signal corresponds to the predetermined type of signaling.

14. The signal detector of claim 13, wherein the predetermined type of signaling is low frequency periodic signaling.

15. The signal detector of claim 11, wherein the generator is configured to: generate the first voltage based on a first current and a second current, the first current to be generated based on the first and second signals of the differential signal, and the second current to be generated based on a common mode reference voltage.

16. The signal detector of claim 15, wherein: the predetermined voltage corresponds to a difference between a first reference voltage and a second reference voltage; and the common mode reference voltage is between the first and second reference voltages.

17. The signal detector of claim 15, wherein the generator is configured to: generate the second voltage based on a third current and a fourth current; the third current to be generated based on a first and second reference voltages; and the fourth current to be generated based on a common mode voltage of the differential signal.

18. The signal detector of claim 17, wherein the predetermined voltage is based on a difference between the first and second reference voltages.

19. The signal detector of claim 11, further comprising: a self-bias circuit coupled to the generator.

20. The signal detector of claim 11, further comprising: an electrostatic discharge circuit coupled to the input.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Additional objects and features of the invention will be more readily apparent from the following detailed description and appended claims when taken in conjunction with the drawings. Although several example embodiments are illustrated and described, like reference numerals identify like parts in each of the figures, in which:

(2) FIG. 1 illustrates an embodiment of a signal detector;

(3) FIG. 2 illustrates another embodiment of a signal detector;

(4) FIGS. 3A-3D illustrate examples of signals for the detectors of FIGS. 1 and 2; and

(5) FIG. 4 illustrates another embodiment of a signal detector.

DETAILED DESCRIPTION

(6) It should be understood that the figures are merely schematic and are not drawn to scale. It should also be understood that the same reference numerals are used throughout the figures to indicate the same or similar parts.

(7) The descriptions and drawings illustrate the principles of various example embodiments. It will thus be appreciated that those skilled in the art will be able to devise various arrangements that, although not explicitly described or shown herein, embody the principles of the invention and are included within its scope. Furthermore, all examples recited herein are principally intended expressly to be for pedagogical purposes to aid the reader in understanding the principles of the invention and the concepts contributed by the inventor(s) to furthering the art and are to be construed as being without limitation to such specifically recited examples and conditions. Additionally, the term, or, as used herein, refers to a non-exclusive or (i.e., and/or), unless otherwise indicated (e.g., or else or or in the alternative). Also, the various example embodiments described herein are not necessarily mutually exclusive, as some example embodiments can be combined with one or more other example embodiments to form new example embodiments. Descriptors such as first, second, third, etc., are not meant to limit the order of elements discussed, are used to distinguish one element from the next, and are generally interchangeable. Values such as maximum or minimum may be predetermined and set to different values based on the application.

(8) In communications application involving standards (e.g., a USB, DP, TBT, CIO) with cables or connectors, LFPS pulses may be detected to enable a high-speed channel for transmitting traffic. In some cases, LFPS signaling may be in the 20-50 MHz range, which by current standards may be relatively low speed. When signals are transmitted based on the CIO standard, LFPS detection should be performed at a fast rate in order to support channel power-up based on less than three pulses (e.g., 3*20 nS=60 nS in worst case). Also, before enabling the channel, the current consumption of the chip (that controls transmission of signals through the interface) should be low.

(9) Example embodiments describe an LFPS detector that operates based on low power in order to support the low-current operation of a chip in order to allow the channel(s) of an interface (e.g., high-speed channel(s)) to be enabled. The LFPS detector may also operate with fast-response time and fast start-up time in order to support a variety of interface standards. In one embodiment, the LFPS detector may consume, for example, a current of 50 uA to 100 uA, may detect LFPS signaling in a duration of less than one pulse, e.g., 20 nS. In these or other embodiments, the LFPS detector may be self-biased and demonstrate improved accuracy, through the use of an integrated rectifier, low current opamp with hysteresis. In these or other embodiments, the LFPS detector may also perform ESD protection without adversely affecting its performance.

(10) FIG. 1 illustrates an embodiment of a signal detector 100 which includes a rectifier 110, a common mode signal generator 120, a reference level generator 130, and an operational amplifier which may operate as a comparator 140. The signal detector 100 also includes a self-bias circuit 150 to provide bias current to the rectifier, common mode generator, and reference level generator. Such a signal detector may be used as an LFPS signaling detector for one or more (e.g., high-speed) channels of an interface, which, for example, may be a USB Type-C cable or an interface based on a DP, TBT, or CIO standard. For the sake of convenience, the interface will be referred to as a USB cable.

(11) The rectifier 110 is coupled to receive a differential input signal Vip and Vin, which, for example, may correspond to the differential signal lines of a high-speed channel of a USB cable, e.g., USB Type-C. In one embodiment, the rectifier 110 include two bipolar junction transistors Q.sub.6 and Q.sub.7 connected in parallel between the self-bias circuit 150 and a node N1. When the bases of transistors Q.sub.6 and Q.sub.7 receive respective signals Vin and Vip of the differential input, currents I.sub.6 and I.sub.7 from the self-bias circuit flow through the transistors and are added at node N1 to form current I.sub.A. Thus, what the rectifier 110 effectively does is transform a differential input signal (Vip, Vin) varying within a predetermined frequency range into a constant-level output voltage determined based on the summed current I.sub.A and the load resistor R.sub.L. In one embodiment, transistors Q.sub.6 and Q.sub.7 may operate in the linear region at this time.

(12) The signals Vin and Vip may be processed in one or more ways before being input into the rectifier 110. For example, the voltages corresponding to signals Vin and Vip may be averaged by a circuit formed by resistors R3 and R4 to generate the common mode voltage V.sub.CM of the differential input signal.

(13) A clamp capacitor CLP may be coupled to the node of the circuit formed by resistors R3 and R4. The clamp capacitor may be charged by the voltage VDD on a supply rail. The voltage stored in the clamp capacitor may be added to the common mode voltage V.sub.CM to ensure that the base-emitter voltages of transistors Q.sub.4 and Q.sub.5 are in an appropriate range to cause these transistors to conduct. Because the output voltage of the clamp capacitor CLP is constant and because transistors Q.sub.4 and Q.sub.5 operate in the linear region at this time, the common mode voltage V.sub.CM controls the amount of current I.sub.4 and I.sub.5 passing through transistors Q.sub.4 and Q.sub.5, which, in turn, controls the value of current I.sub.B, which plays a role in the output of the detector as described in greater detail below.

(14) The resistors R3 and R4 may have resistance values sufficient to provide electrostatic discharge (ESD) protection (e.g., secondary ESD) for the detector. For example, when the differential input signal (Vip,Vin) becomes excessively large as the result of an applied electrostatic charge, the resistors R3 and R4 may dissipate a significant portion of this charge to prevent an excessive voltage from being input into the bases of transistors Q.sub.4 and Q.sub.5. Without resistors R3 and R4, these transistors may be damaged. In one case, the common mode voltage line 15 of transistors Q.sub.4 and Q.sub.5 may be sufficiently close to the common mode voltage line 25 of transistors Q.sub.2 and Q.sub.3 that these transistors may also be damaged by the electrostatic charge as a result of parasitic coupling. Thus, resistors R3 and R4 may service to provide extra ESD protection for all four transistors Q.sub.2, Q.sub.3, Q.sub.4, and Q.sub.5. In one embodiment, the sizes of Q.sub.2 and Q.sub.3 may not be large enough to support self-robustness.

(15) The differential input signal (Vip,Vin) may be coupled to the rectifier 110 through a respective number of resistors R1 and R2. Resistors R1 and R2 may perform secondary ESD protection for transistors Q.sub.6 and Q.sub.7. These resistors also effectively form a soft low-pass filter that may help the input signal and its common mode component (generated by R3 and R4) to track each other better. In one embodiment, the resistors R1 and R2 may have the same resistance values and/or resistors R3 and R4 may have the same resistance values.

(16) The node N1 at the output of the rectifier is coupled to a parallel RC circuit 170 formed from resistor R.sub.L and capacitor C.sub.L. This circuit operates as a filter to suppress any ripple voltage that may be present in the output of the rectifier 110, which ripple voltage may adversely affect voltage Von and thus the output of the comparator 140 which is responsible for indicating the detection result. Additionally, the current I.sub.A through the resistor R.sub.L is partially used to set the voltage levels at nodes N2 and N3, which, in turn, are used to determine the output of the detector, e.g., detect low frequency periodic signaling on the channel associated with the differential input line.

(17) As illustrated in FIG. 1, the voltage formed at node N1 sets the voltage input into the inverting terminal () of the operational amplifier forming comparator 140. The voltage at node N1 also helps to form the voltage input into the non-inverting terminal (+). The voltage at node N1 is based on the sum of the current I.sub.A output from the rectifier 110 and a current I.sub.C output from circuit 128 of the common mode signal generator 120. The sum of these currents generates the voltage Von, at nodes N2 and N3, based on the value of resistor R.sub.L.

(18) Circuit 128 of the common mode signal generator includes transistors Q.sub.2 and Q.sub.3 coupled in parallel between node N1 and the self-bias circuit 150. The transistors Q.sub.2 and Q.sub.3 control the value of the current I.sub.c based on a sum of the currents I.sub.2 and I.sub.3 passing through transistors Q.sub.2 and Q.sub.3. The values of the currents I.sub.2 and I.sub.3 passing through transistors Q.sub.2 and Q.sub.3 are based on a common mode reference voltage V.sub.REF,CM. The common mode reference voltage V.sub.REF,CM may be predetermined and set based on the current from the self-bias circuit 150 and the values of resistors R5, R6, and R7. Using these resistance values, the voltages V.sub.REF,H and V.sub.REF,L may be set, which, in turn, sets the common mode reference voltage V.sub.REF,CM used to determine the amount of current I.sub.C. The value of I.sub.C may be considered a reference current, which may have a constant value for fixed values of R5, R6, and R7. The reference current I.sub.C is added to the current I.sub.A output from the rectifier 110 (which is proportional to the difference between Vip and Vin of the differential input signal) in order to set the node voltage Von at nodes N2 and N3. (Transistors as described herein may operate in the linear region when, for example, (V.sub.REF,HV.sub.REF,L)/2 is much less than V.sub.be0.7V.)

(19) In one embodiment, the values of R6 and R7 may be set so that the common mode reference voltage V.sub.REF,CM corresponds to an average of V.sub.REF,H and V.sub.REF,L. This average may be predetermined, for example, based on the intended application of the signal detector. For example, the common mode reference voltage V.sub.REF,CM may be set to corresponding to one or more operating parameters of a USB Type-C cable, for purposes of detecting an LFPC signal on a high-speed channel. The detection of an LFPS signal may, for example, be input into a controller for powering up or activating the high-speed channel.

(20) Circuit 124 of the common mode generator includes transistors Q.sub.4 and Q.sub.5 coupled in parallel between node N4 and the self-bias circuit 150. The transistors Q.sub.4 and Q.sub.5 control the value of the current I.sub.B based on a sum of the currents I.sub.4 and I.sub.5 passing through transistors Q.sub.4 and Q.sub.5. The values of the currents I.sub.4 and I.sub.5 are based on the common mode voltage V.sub.CM input into the bases of Q.sub.4 and Q.sub.5. Because the common mode voltage V.sub.CM is generated based on a difference between the differential signals of the input signal, current I.sub.B (which corresponds to the sum of I.sub.4 and I.sub.5) is proportional to the common mode voltage, which makes current I.sub.B a useful component in detecting LFPS signaling.

(21) Circuit 135 of the reference level generator 130 generates a current I.sub.D, which is added to current I.sub.B for performing LFPS signaling detection. Circuit 135 includes transistors Q.sub.0 and Q.sub.1 connected in parallel and coupled between node N4 and the self-bias circuit 150. Transistors Q.sub.0 and Q.sub.1 pass currents I.sub.0 and I.sub.1 when voltages V.sub.REF,H and V.sub.REF,L are respectively coupled to their bases. As previously explained, the values of resistors R5, R6, and R7 may be selected to control the values of these currents. Thus, in one embodiment, current I.sub.D may have a fixed value that serves as a reference current that is added to current I.sub.C to form voltage Vop at node N4.

(22) The node N4 is coupled to a parallel RC circuit 180 formed from resistor R.sub.L and capacitor C.sub.L. Parallel RC circuit 180 is coupled between the rail of supply voltage VDD and node N4 and may be the same or different from the parallel RC circuit 170 previously discussed. Circuit 180 operates as a filter to suppress any ripple voltage that may be present in the signal received at node N4.

(23) The supply voltage VDD may be provided to enable operation of the common mode reference generator 130 and the reference level generator 140 based on enable signal EN. This enable signal EN is coupled to the gate of a PMOS transistor 198 and, for example, may be generated when the state of the channel corresponding to the input signal is in an unpowered or inactive state. In this case, the detector may be enabled to detect LFPS signaling for purpose re-powering or re-activating the channel when, for example, a USB cable is coupled to a host or connected device. A controller of the host or connected device may generate the enable signal.

(24) In one embodiment, the same enable signal EN may be used to power the self-bias circuit 150. The enable signal EN may be coupled to the gates of a PMOS transistor 190 and an NMOS transistor 195. When the enable signal EN has a first value, the detector may be disabled. When the enable signal EN has a second value, the detector may be enabled. The first and second values may be based, for example, on the type of transistors used, e.g., NMOS or PMOS.

(25) The comparator 140 generates a detection signal relative to the differential input line (Vip,Vin) based on the voltage Von at node N2 and the voltage at node N4. The detection signal may have a first value to indicate the presence of a certain type of signaling or signal on the input and may have a second value to indicate the absence of the certain type of signaling or signal. The certain type of signaling may be, for example, LFPS signaling or another type of signal or signaling or condition in a host circuit and/or one or more of its communication channels.

(26) In operation, any difference |VipVin| between the components of the differential signal input into rectifier 110 translates into differences in the voltages applied to the bases of transistors Q.sub.6 and Q.sub.7, and this is so whether the difference is positive or negative, e.g., whether Vip>Vin or Vin>Vip. When a difference |VipVin|0 exists, that difference will cause more current to flow into transistors Q.sub.6 and Q.sub.T. When |VipVin| increases, current I.sub.A=I.sub.6+I.sub.7 increases.

(27) When the signal detector is enabled (EN) and LFPS signaling exists on the differential input line of the channel, the rectifier 110 rectifies the differential input signal. When |VipVin| is less than the difference between the reference voltages V.sub.REF,H and V.sub.REF,L (that is, when |VipVin|<(V.sub.REF,HV.sub.REF,L)), then Vop at node N4 is greater than Von at node N3, e.g., Vop>Von. When Vop>Von, then the voltage applied to the non-inverting terminal of comparator 140 is negative and thus less than the voltage Von applied to the inverting terminal of the comparator 140 from node N2. As a result, the signal LFPS_detect_out generated at the output of the comparator has a value indicative of the detection of LFPS signaling on the input line of the channel.

(28) In at least one embodiment, a filter may be coupled between node N3 and node N4 in order to suppress noise. The filter may include a capacitor CF operating as a low-pass filter to remove high-frequency components or other spurious signals that might be coupled to the differential input signal or which might otherwise be present, for example, as the result of electromagnetic interference, parasitic coupling from the signal lines of an adjacent channel, and/or other effects.

(29) When the signal detector is enabled (EN) and the |VipVin|(V.sub.REF,HV.sub.REF,L), which, for example, corresponds to the case where the difference between Vip and Vin, is equal or close to the trip point of the detector, then I.sub.7I.sub.0, I.sub.6I.sub.1, and I.sub.5I.sub.4I.sub.3I.sub.2. As a result, VonVop. When the signal detector is enabled and |VipVin| is not equal (or approximately equal) to (V.sub.REF,HV.sub.REF,L), then the output of the signal detector is either a logical 1 or a logical 0.

(30) When the signal detector is enabled (EN) and the input into rectifier 110 includes LFPS signaling that is larger than the threshold reference value, then |VipVin|>(V.sub.REF,HV.sub.REF,L). As a result, the following currents are produced in the signal detector (where I.sub.tail corresponds to the current output from the self-bias circuit and ac corresponds to a predetermined constant value less than 1:
I.sub.7+I.sub.6I.sub.tail(1)
I.sub.5I.sub.40(2)
I.sub.3+I.sub.22**I.sub.tail/2(3)
I.sub.1+I.sub.02*(1)*I.sub.tail/2(4)

(31) Based on these currents, the following currents are produced:
I.sub.A=I.sub.7+I.sub.6I.sub.tail(5)
I.sub.B=I.sub.5+I.sub.40(6)
I.sub.C=I.sub.3+I.sub.2*I.sub.tail(7)
I.sub.D=I.sub.1+I.sub.0(1)*I.sub.tail(8)

(32) Given these currents, the following voltages are produced at nodes N2, N3, and N4:
Von=(I.sub.A+I.sub.C)*Z.sub.L(1+)*I.sub.tail*Z.sub.L(9)
Vop=(I.sub.B+I.sub.D)*Z.sub.L(1)*I.sub.tail*Z.sub.L(10)
In the above equations, the parameter may be a predetermined constant with a value less than 1. Consider the example where =0.25. Then, Von=1.25*I.sub.tail*Z.sub.L and Vop=0.75*I.sub.tail*Z.sub.L, where Z.sub.L corresponds to the impedance of the input line. Because the quantity I.sub.tail*Z.sub.L is the same in both equations, Von>Vop. When Von>Vop, the LFPS_detect_out signal of the comparator 140 corresponds to a value which indicates the presence of LFPS on the input line. In some cases, the comparator 140 may have some hysteresis to reject noise while amplifying the (VonVop) difference signal to a CMOS level output.

(33) When the signal detector is enabled (EN) and there is no LFPS on the input line, then the following currents exist. In this case, <1 and, for example, may be a value of 0.5.
I7=I6=I5=I4=I.sub.tail/4(11)
I3=I2=*I.sub.tail/4,(12)
I.sub.1=(1+)*I.sub.tail/4+gm Vref(13)
I.sub.0=(1+)*I.sub.tail/4gm*Vref(14)

(34) In this case, V.sub.REF,HV.sub.REF,L=2*Vref and (V.sub.REF,H+V.sub.REF,L)/2=V.sub.REF,CM. These values cause the comparator 140 to output an LFPS_detect_out signal with a value of 0, indicating that no LFPS has been detected on the input line, at least not yet.

(35) The self-bias circuit 150 includes a transistor Q.sub.10 and a transistor Q.sub.11 to control output of the tail current I.sub.tail to the rectifier 110, common mode signal generator 120, and the reference signal generator 130 based on enable signal EN (and the complement of this signal, ENB). The transistor Q.sub.10 may be, for example, a PMOS transistor and transistor Q.sub.11, may be, for example, an NMOS transistor.

(36) When the enable signal ENB is at a logical 0 level, PMOS transistors Q.sub.10 and Q.sub.12 (198) and NMOS transistor Q.sub.11 turn on and current flows from supply voltage VDD through resistors R10, R11, and R12 of the self-bias circuit 150. As a result, the voltage at the node between R11 and R12 turns on the first-tier transistors Q.sub.A, and the logical 1 value of enable signal EN turns on transistor Q.sub.11 at this time, thereby generating the tail current I.sub.tail. The logical 0 level of the ENB signal couples the reference resistors R5, R6, and R7 to VDD, to thereby generate reference voltages V.sub.REF,HV.sub.REF,CM, and V.sub.REF,L.

(37) When the enable signal EN is at a logical 1 level (and thus ENB is at logical 0 level), transistors Q.sub.10, Q.sub.11, and Q.sub.12 turn on. As a result, the reference signal generator 130 is enabled (on) and transistors QA and QB (which correspond to current mirrors) generate current I.sub.tail for the rectifier 110 and the reference signal generator 130. In this state, the signal detector is enabled to detect, for example, LFPS signaling.

(38) FIG. 2 illustrates another embodiment of a signal detector which may be the same as the signal detector of FIG. 1, except that the common mode generator 230 includes additional transistors. For example, one or more transistors n*Q transistors may be coupled in parallel to transistors Q.sub.4 and Q.sub.5 and m*Q transistors may be coupled in parallel to transistors Q.sub.2 and Q.sub.3. The bases of the additional n*Q transistors are coupled to the common mode voltage V.sub.CM, and the bases of the additional m*Q transistors are coupled to the common mode reference voltage V.sub.REF,CM. The values of n and m may be the same or different, where n1 and m1.

(39) The additional transistors may reduce the tail current through the transistors by a proportional amount, but may increase the gain of the common mode signal generator 220 relative to the signal detector of FIG. 1. For example, adding two additional transistors to each side of the common mode signal generator may increase the gain by a factor of 2 without increasing the current, because all of the divided tail currents are summed at the same node. In one embodiment, extra parasitic capacitance generated by the additional transistors may supplement the filtering performed by capacitors CF and CL. As a result, the capacitances of CL and CF may be adjusted to lower values in order to compensate for the extra parasitic capacitors of the additional common mode transistors. Adding the additional transistors will not increase the size or chip space of the detector by any appreciable amount, but may improve gain significantly.

(40) FIGS. 3A to 3D illustrate examples of input and output signals and waveforms generated by the signal detector of FIG. 1. The vertical dotted line separates a period when the signal detector is enabled but no LFPS signaling has been detected on the input line, e.g., when the LFPS_detect_out signal has a first value, e.g., 0. The period after the vertical dotted line corresponds to when the signal detector is enabled and an LFPS signaling has been detected on the input line, e.g., when the LFPS_detect_out has a second value, e.g., 1. Also, the signals illustrated as solid lines correspond to the signal detector of FIG. 1. The signals with dotted lines correspond to the signal detector of FIG. 2.

(41) During the period before an LFPS signal is received, in FIG. 3A, the components of the differential input signal (Vip, Vin) have a nominally zero value which lies between the high and low reference values, V.sub.REF,H and V.sub.REF,L. In one embodiment, Vip and Vin may equal the common mode reference voltage V.sub.REF,CM.

(42) In FIG. 3B, the currents I.sub.6 and I.sub.7 through transistors Q.sub.6 and Q.sub.7 of the rectifier 110 are nominally zero, the currents I.sub.4 and I.sub.5 through transistors Q.sub.4 and Q.sub.5 equal I.sub.tail/4, and the currents I.sub.2 and I.sub.3 through transistors Q.sub.2 and Q.sub.3 are at a constant value of *I.sub.tail/4 because I.sub.tail is a constant value and the parameter is fixed. Also, the currents I.sub.0 and I.sub.1 through transistors Q.sub.0 and Q.sub.1 are at constant values that respectively correspond to (1+)*I.sub.tail/4gm*V.sub.ref and (1+)*I.sub.tail/4+gm V.sub.REF, where gm is the transconductance of the transistor(s) of the comparator 140 and V.sub.F=(V.sub.REF,HV.sub.REF,L).

(43) In FIG. 3C, the values Vop and Von are constant values. When there is no LFPS signaling, the input signal level<V.sub.REF=(V.sub.REF,HV.sub.REF,L) and Von=VDDR.sub.L*(I.sub.A+I.sub.C) and Vop=VDDR.sub.L*(I.sub.B+I.sub.D).

(44) In FIG. 3D, the LFPS detector properly outputs an LFPS_detect_out signal with a first value (e.g., logical 0) indicating that LFPS signaling has not been detected on the input line.

(45) During the period after an LFPS signal is received, in FIG. 3A, the components of the differential input signal (Vip, Vin) are out of phase by and oscillate between positive and negative values that may be greater than the high and low reference values, V.sub.REF,H and V.sub.REF,L. The frequency of Vip and Vin signal components may be determined, for example, by the channel frequency.

(46) In FIG. 3B, the currents I.sub.6 and I.sub.7 through transistors Q.sub.6 and Q.sub.7 are rectified into what are effectively square waves of the same period as the differential components of the input signal and with a phase shift of . As a result, currents I.sub.6 and I.sub.7 have a first value in the first half of the cycle and a second value in the second half of the cycle. Also, in FIG. 3B, each of the currents I.sub.4 and I.sub.5 through transistors Q.sub.4 and Q.sub.5 transition to a value lower than I.sub.tail/4 based on the common mode voltage V.sub.CM output from the filter formed by resistors R3 and R4. The currents I.sub.0, I.sub.1, I.sub.2, and I.sub.3 remain constant at the same values as during the period before the LFPS signal was received.

(47) In FIG. 3C, the values Vop and Von change and actually invert to a point where Vop>Von.

(48) In FIG. 3D, the values of Vop and Von cause the comparator 140 of the signal detector to output a second value (e.g., logical 1) indicating the presence of LFPS signaling on the input line.

(49) FIG. 3C also illustrates example results obtained for the signal detector of FIG. 2. In the signal detector of FIG. 2, the value of a is larger than the value of in the signal detector of FIG. 1. Therefore, the gain of the comparator is higher than the gain of the signal detector of FIG. 1. This produces greater values for Vop and Von (see dashed curves) and earlier detection of LFPS signaling (e.g., by a number of nanoseconds), as indicated by the dashed line in (D). As a result, the current of the comparator in the embodiment of FIG. 2 may be reduced without sacrificing performance.

(50) In accordance with one embodiment, a signal detector includes an input, a generator, and an output stage. These features are illustrated in the embodiments of FIGS. 1 and 2. For example, the input may receive a differential signal (Vip, Vin). The generator may generate a first voltage (V.sub.1) based on the differential signal and a second voltage (V.sub.2) based on the first voltage and a predetermined voltage (e.g., the voltage Vop at node N4 is generated based on the difference between V.sub.REF,H and V.sub.REF,L which control current through Q.sub.0 and Q.sub.1, respectively). The output stage may output a detection signal (LFPS_detect_out) based on the first voltage and the second voltage. The detection signal may have a first value when a difference between the first and second signals is in a first range (e.g., when |VipVin|<(V.sub.REF,HV.sub.REF,L)) and may have a second value when the difference between the first and second signals is in a second range (e.g., when |VipVin|>(V.sub.REF,HV.sub.REF,L)). The first value of the detection signal may indicate that the differential signal does not correspond to a predetermined type of signaling, and the second value of the detection signal may indicate that the differential signal corresponds to the predetermined type of signaling. The predetermined type of signaling may be low frequency periodic signaling or another type of signal or signaling.

(51) FIG. 4 illustrates another embodiment of a signal detector which may be used, for example, for detecting LFPS signaling. The signal detector of this embodiment may be the same as the signal detector of FIG. 2, except that MOS transistors are used to implement the rectifier 310, the common mode signal generator 320, and the reference signal generator 330. As illustrated in FIG. 4, the MOS transistors may be NMOS transistors having gates connected in a manner analogous to the bases of the bipolar transistors in FIG. 2.

(52) In accordance with one or more of the aforementioned embodiments, a signal detector includes a rectifier that generates a first current based on an input signal, a first circuit that generates a second current based on a first reference signal, a second circuit that generates a third current based on a common mode voltage, a reference signal generator that generates a fourth current based on a second reference signal and a third reference signal, and a comparator that generates a detection signal based on the first current, the second current, the third current, and the fourth current. The detection signal may be generated to detect low frequency periodic signaling or another type of signal on a communication line. The communication line may be, for example, a channel of an interface.

(53) In one embodiment, the signal detector may be used in a redriver for a USB, DP, TBT, or CIO mode application. Such a redriver may be limiting or linear, and the signal detector may be implemented without providing extra bias because of the self-bias circuit. In one embodiment, all or a portion of the reference signals may be generated from bias. The hysteresis in the comparator may reduce the sensitivity of the signal detector to supply noise, and in some cases may make the signal detector immune to such noise. In addition to interface applications, the signal detector may be used in other applications, where, for example, a fast response squelch detector is to be implemented.

(54) In addition to the aforementioned features, the self-biased circuit of the embodiments disclosed herein may allow for improved performance, for example, by helping the chip of the signal detector to maintain a low-power savings mode. In one embodiment, each of the left and right reference branches of the common mode signal generator may take a current of 10 uA, while each of the other two branches (e.g., the rectifier circuit and the reference level generator) may take a current of 20 uA. Other performance benefits of the signal detector embodiments include, but are not limited to, fast-response time, fast power-up, low-current and low-power operation, improved detection accuracy, integrated hysteresis, the use of an integrated rectifier and integrated comparator, and built-in secondary ESD protection.

(55) The controllers, filters, generators, stages, inputs, rectifiers, and other signal-generating and signal-processing features of the embodiments disclosed herein may be implemented in logic which, for example, may include hardware, software, or both. When implemented at least partially in hardware, the controllers, filters, generators, stages, inputs, rectifiers, and other signal-generating and signal-processing features may be, for example, any one of a variety of integrated circuits including but not limited to an application-specific integrated circuit, a field-programmable gate array, a combination of logic gates, a system-on-chip, a microprocessor, or another type of processing or control circuit.

(56) When implemented in at least partially in software, the controllers, filters, generators, stages, inputs, rectifiers, and other signal-generating and signal-processing features may include, for example, a memory or other storage device for storing code or instructions to be executed, for example, by a computer, processor, microprocessor, controller, or other signal processing device. The computer, processor, microprocessor, controller, or other signal processing device may be those described herein or one in addition to the elements described herein. Because the algorithms that form the basis of the methods (or operations of the computer, processor, microprocessor, controller, or other signal processing device) are described in detail, the code or instructions for implementing the operations of the method embodiments may transform the computer, processor, controller, or other signal processing device into a special-purpose processor for performing the methods described herein.

(57) The benefits, advantages, solutions to problems, and any element(s) that may cause any benefit, advantage, or solution to occur or become more pronounced are not to be construed as a critical, required, or essential features or elements of any or all the claims. The invention is defined solely by the appended claims including any amendments made during the pendency of this application and all equivalents of those claims as issued.

(58) Although the various exemplary embodiments have been described in detail with particular reference to certain exemplary aspects thereof, it should be understood that the invention is capable of other example embodiments and its details are capable of modifications in various obvious respects. As is readily apparent to those skilled in the art, variations and modifications can be affected while remaining within the spirit and scope of the invention. Accordingly, the foregoing disclosure, description, and figures are for illustrative purposes only and do not in any way limit the invention, which is defined only by the claims.