A signal receiving device adapting to a signal input mode and a signal processing method for the same are provided. The signal receiving device can determine various signal input modes, such as a differential signal or a single-ended signal, and select an appropriate signal source, such that the signal receiving device can not only receive the input signal correctly, but also adjust the received input signal to a differential signal with the same amplitude and opposite phases to make subsequent data analysis work easier.

A signal receiving device adapting to a signal input mode and a signal processing method for the same are provided. The signal receiving device can determine various signal input modes, such as a differential signal or a single-ended signal, and select an appropriate signal source, such that the signal receiving device can not only receive the input signal correctly, but also adjust the received input signal to a differential signal with the same amplitude and opposite phases to make subsequent data analysis work easier.

A signal detection circuit includes: a first DC voltage remover that removes a DC voltage from an input differential signal; a limiting amplifier that adjusts an amplitude of the input differential signal; a reset signal generator that generates an internal reset signal on the basis of the input differential signal obtained after the amplitude is adjusted; a first bias voltage applying unit that generates a differential signal for detection by applying a bias voltage to the signal from which the DC voltage is removed; and a flip-flop circuit that generates a packet detection signal by holding a state indicating input of a packet signal on the basis of the differential signal for detection and releasing the holding on the basis of the internal reset signal. The reset signal generator includes: a differential single-phase conversion circuit; a voltage holding circuit; and a voltage comparison circuit.

A signal receiver circuit includes a first amplification circuit and an offset compensation circuit. The first amplification circuit generates a first amplified signal and a second amplified signal by amplifying an input signal and a reference voltage. The offset compensation circuit adjusts voltage levels of the first and second amplified signals based on a DC level of the input signal and a voltage level of the reference voltage.

To obtain a communication apparatus capable of reducing the consumption of electric power.

A communication system according to the present disclosure includes a transmitter that generates a first signal including communication data and sends the first signal through a communication terminal in a first operation mode, and that generates a second signal including a predetermined first signal pattern and having a transition rate lower than the first signal and sends the second signal through the communication terminal in a second operation mode, and a controller that sets an operation mode for the transmitter to either of a plurality of operation modes including the first operation mode and the second operation mode.

A communication interface comprises an input terminal (Rx) for receiving a logic signal from a remote interface (IF2); a logic level discriminator (12) coupled to the input terminal; a peak detector (14) connected to store the peak value of the signal at the input terminal; and a voltage follower (16) connected to the discriminator for providing an auxiliary supply voltage (Vdd2) based on the value provided by the peak detector. An electrostatic discharge (ESD) protection device is further provided, including a first diode (D1) and an RC-circuit forming the peak detector, connected in series between the input terminal (Rx) and a first power supply line (Vss1); a transistor (MN1) connected between the first power supply line (Vss1) and the input terminal (Rx) through the first diode (D1) or a second diode (D1); and inverter (42) configured to turn on the transistor when the voltage across the capacitor of the RC-circuit is less than a threshold.

After transmitting first electrical signals to a receiver, a transmitter receives a burst absent mode signal from the receiver. While in a ready state, the transmitter receives a signal including a data burst, converts the signal to second electrical signals, including a settled DC offset, and transmits the second electrical signals to the receiver. The receiver transmits the burst absent mode signal to the transmitter after receiving the first electrical signals, detects a presence of the second electrical signals. In response to detecting the presence of the second electrical signals, the receiver removes the DC offset from the second electrical signals to generate output signals, and causes transmitting the output signals to a subsequent device. The receiver removes the DC offset by causing an instruction to discharge AC coupling capacitors. The burst absent mode signal is generated using a host reset instruction or an internally generated instruction.

A method and apparatus for a novel adaptive equalization technique for a Serializer/Deserializer receiver is disclosed. In one approach, adjustment of AC and DC gains is performed before DFE coefficients are adjusted. Further after the equalization an electrical idle threshold may be set based on the results of the equalization.

A communication interface comprises an input terminal (Rx) for receiving a logic signal from a remote interface (IF2); a logic level discriminator (12) coupled to the input terminal; a peak detector (14) connected to store the peak value of the signal at the input terminal; and a voltage follower (16) connected to the discriminator for providing an auxiliary supply voltage (Vdd2) based on the value provided by the peak detector. An electrostatic discharge (ESD) protection device is further provided, including a first diode (D1) and an RC-circuit forming the peak detector, connected in series between the input terminal (Rx) and a first power supply line (Vss1); a transistor (MN1) connected between the first power supply line (Vss1) and the input terminal (Rx) through the first diode (D1) or a second diode (D1); and inverter (42) configured to turn on the transistor when the voltage across the capacitor of the RC-circuit is less than a threshold.

An electronic device includes an analog front end (AFE) circuit including plural modules, and a processor that provides a user interface for a firmware update, determines a target module, of which offset calibration is to be performed, among the plural modules, based on a user input to the user interface, determines a position within in the AFE circuit to which a common mode voltage is to be applied to perform the offset calibration of the target module, and determines an offset calibration sequence including the target module and the position.