An apparatus is described that includes a receiver. The receive includes a data sampler, a positive error sampler and a negative error sampler each having respective inputs coupled to a same differential channel. The receiver also includes circuitry to drive the respective inputs, the circuitry to place a same calibration voltage on the differential channel to calibrate each of the data sampler, positive error sampler and negative error sampler with the same calibration voltage.

A method and apparatus for a novel adaptive equalization technique for a Serializer/Deserializer receiver is disclosed. In one approach, adjustment of AC and DC gains is performed before DFE coefficients are adjusted. Further after the equalization an electrical idle threshold may be set based on the results of the equalization.

Described is an apparatus which comprises: a first capacitor coupled to a first input pad; a second capacitor coupled to second input pad; a first resistor coupled to the second capacitor; a third capacitor coupled in series with the first resistor; a second resistor coupled in series with the third capacitor and also coupled to the first capacitor; and a differential amplifier coupled to the first and second capacitors and to the first and second resistors.

The invention relates to a reception device, etc., applied to a transmission/reception system capable of performing high-speed transmission, having a structure to enable to adjust an offset without increasing a circuit area and power consumption. The reception device includes a signal input unit including an offset adjusting circuit, and an adjustment unit. When a pair of adjusting signals of which a voltage between signals is fixed to zero V is outputted from a transmission device to the reception device connected to each other via a differential signal line including at least a pair of signal lines, the signal input unit that has received the pair of adjusting signals outputs logical value data corresponding to the voltage between signals. The adjustment unit determines adjustment value data to adjust the offset of a threshold to obtain the logical value data based on the logical value data inputted in a certain period.

An apparatus is described that includes a receiver. The receive includes a data sampler, a positive error sampler and a negative error sampler each having respective inputs coupled to a same differential channel. The receiver also includes circuitry to drive the respective inputs, the circuitry to place a same calibration voltage on the differential channel to calibrate each of the data sampler, positive error sampler and negative error sampler with the same calibration voltage.

An integrated circuit device includes an output driver having a data signal terminal, logic circuitry, and a driver circuit coupled to the logic circuitry and data signal terminal. The driver circuit is configured to drive a signal corresponding to a symbol onto the data signal terminal, wherein the symbol is an N-bit symbol, having one of 2N predefined values, N is an integer greater than 1, and the signal corresponding to the symbol has one of 2N signal levels. The driver circuit includes first, second and third driver sub-circuits, each driven by an input corresponding to one or more bits of the N-bit symbol, wherein the second and third driver sub-circuits are weighted, relative to the first driver sub-circuit, to reduce gds distortion in the signal.

A receiver includes a signal receiving part suitable for outputting a signal corresponding to a reception signal that is received through an input terminal, and controlling a DC voltage of a signal to be outputted, according to an offset signal, an amplifying part suitable for amplifying and outputting an output of the signal receiving part, and a feedback control part suitable for controlling the offset signal according to an output of the amplifying part.

In some embodiments, a differential amplifier with duty cycle correction is provided.

After transmitting first electrical signals to a receiver, a transmitter receives a burst absent mode signal from the receiver. While in a ready state, the transmitter receives a signal including a data burst, converts the signal to second electrical signals, including a settled DC offset, and transmits the second electrical signals to the receiver. The receiver transmits the burst absent mode signal to the transmitter after receiving the first electrical signals, detects a presence of the second electrical signals. In response to detecting the presence of the second electrical signals, the receiver removes the DC offset from the second electrical signals to generate output signals, and causes transmitting the output signals to a subsequent device. The receiver removes the DC offset by causing an instruction to discharge AC coupling capacitors. The burst absent mode signal is generated using a host reset instruction or an internally generated instruction.

The invention relates to a reception device, etc., applied to a transmission/reception system capable of performing high-speed transmission, having a structure to enable to adjust an offset without increasing a circuit area and power consumption. The reception device includes a signal input unit including an offset adjusting circuit, and an adjustment unit. When a pair of adjusting signals of which a voltage between signals is fixed to zero V is outputted from a transmission device to the reception device connected to each other via a differential signal line including at least a pair of signal lines, the signal input unit that has received the pair of adjusting signals outputs logical value data corresponding to the voltage between signals. The adjustment unit determines adjustment value data to adjust the offset of a threshold to obtain the logical value data based on the logical value data inputted in a certain period.