A receiver includes a signal receiving part suitable for outputting a signal corresponding to a reception signal that is received through an input terminal, and controlling a DC voltage of a signal to be outputted, according to an offset signal, an amplifying part suitable for amplifying and outputting an output of the signal receiving part, and a feedback control part suitable for controlling the offset signal according to an output of the amplifying part.

A transmission/reception method and device for isolated communication is proposed. The transmission/reception method includes performing transmission, wherein bit streams are extracted from data and two or more predetermined number of bits are modulated into one DC balanced symbol so as to generate a signal in which a plurality of symbols are listed, thereby transmitting the signal through an isolated communication circuit, and performing reception, wherein the signal is received through the isolated communication circuit and the plurality of symbols included in the signal are demodulated into the two or more predetermined number of bits so as to generate the bit streams and organize the bit streams into the data. The transmission/reception method and device may reduce power consumption at the same communication speed because a plurality of bits is represented by the one DC balanced symbol.

An on-chip AC coupled receiver with baseline wander compensation. The receiver may be used for either single ended or differential signals. The receiver includes an input terminal to receive an input signal. AC coupling circuitry is between the input terminal and a node and couples the input signal into a coupled signal at the node. A control loop senses low frequency signal content at the node and uses a linear buffer in adjusting the coupled signal at the node based on the low frequency signal content. The operation of the control loop compensates for potential baseline wander in the coupled signal. An input stage to recovers data from the coupled signal at the node.

Described is an apparatus which comprises: an amplifier; and a passive continuous-time linear equalizer integrated with a baseline wander (BLW) corrector, wherein the integrated equalizer and BLW corrector is coupled to the amplifier.

An integrated circuit device includes an output driver having a data signal terminal, logic circuitry, and a driver circuit coupled to the logic circuitry and data signal terminal. The driver circuit is configured to drive a signal corresponding to a symbol onto the data signal terminal, wherein the symbol is an N-bit symbol, having one of 2N predefined values, N is an integer greater than 1, and the signal corresponding to the symbol has one of 2N signal levels. The driver circuit includes first, second and third driver sub-circuits, each driven by an input corresponding to one or more bits of the N-bit symbol, wherein the second and third driver sub-circuits are weighted, relative to the first driver sub-circuit, to reduce gds distortion in the signal.

An on-chip AC coupled receiver with baseline wander compensation. The receiver may be used for either single ended or differential signals. The receiver includes an input terminal to receive an input signal. AC coupling circuitry is between the input terminal and a node and couples the input signal into a coupled signal at the node. A control loop senses low frequency signal content at the node and uses a linear buffer in adjusting the coupled signal at the node based on the low frequency signal content. The operation of the control loop compensates for potential baseline wander in the coupled signal. An input stage to recovers data from the coupled signal at the node.

Described is an apparatus which comprises: an amplifier; and a passive continuous-time linear equalizer integrated with a baseline wander (BLW) corrector, wherein the integrated equalizer and BLW corrector is coupled to the amplifier.

A signal on a transmitter tracks noise on a ground node in a manner decoupled from a positive node of a power supply. The signal is transmitted from the transmitter to the receiver. A reference voltage is generated on the receiver to track noise on a ground node in the receiver. Consequently, the received signal and the reference voltage have substantially the same noise characteristics, which become common mode noise that can be cancelled out when these two signals are compared against each other. In a further embodiment, the reference voltage is compared against a predetermined calibration pattern. An error signal is generated based on a difference between the sampler output and the predetermined calibration pattern. The error signal is then used to adjust the reference voltage so that the DC level of the reference voltage is positioned substantially in the middle of the received signal.

An integrated circuit device includes a sense amplifier with an input to receive a present signal representing a present bit. The sense amplifier is to produce a decision regarding a logic level of the present bit. The integrated circuit device also includes a circuit to precharge the input of the sense amplifier by applying to the input of the sense amplifier a portion of a previous signal representing a previous bit. The integrated circuit device further includes a latch, coupled to the sense amplifier, to output the logic level.

In an identification information receiving device that receives identification information defined by a plurality of bits and superimposed on a current or a voltage of a power line by an identification information transmitting device that is connected to the identification information receiving device via the power line, an integration circuit integrates an input signal that indicates a voltage value corresponding to the current or the voltage of the power line. A subtraction circuit subtracts an output signal of the integration circuit from the input signal. A binary converter determines 1 when an output signal of the subtraction circuit is greater than or equal to a threshold value, and determines 0 when the output signal of the subtraction circuit is less than the threshold value.