A transceiver architecture supports high-speed communication over a signal lane that extends between a high-performance integrated circuit (IC) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers. The architecture compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex transmit and receive equalization circuitry on the higher-performance side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated based upon the signal response at the receiver of the higher-performance IC.

A memory interface may include a transmitter that generates multi-level signals. The transmitter may employ channel equalization to improve the quality and robustness of the multi-level signals. The channel equalization may be controlled independently from the drive strength of the multi-level signals. For example, a first control signal may control the de-emphasis or pre-emphasis applied to a multi-level signal and a second control signal may control the drive strength of the multi-level signal. The first control signal may control a channel equalization driver circuit and the second control signal may control a driver circuit.

A memory interface may include a transmitter that generates multi-level signals. The transmitter may employ channel equalization to improve the quality and robustness of the multi-level signals. The channel equalization may be controlled independently from the drive strength of the multi-level signals. For example, a first control signal may control the de-emphasis or pre-emphasis applied to a multi-level signal and a second control signal may control the drive strength of the multi-level signal. The first control signal may control a channel equalization driver circuit and the second control signal may control a driver circuit.

An equalizer circuit includes a first arithmetic circuit, a second arithmetic circuit, a data sampling circuit, and an edge sampling circuit. The first arithmetic circuit is configured to compensate an equalization sequence by secondary feedback sequences to output a first added sequence. The second arithmetic circuit is configured to compensate the first added sequence by a primary feedback sequence to output a second added sequence. The data sampling circuit samples, according to data clock, the second added sequence to output a primary sequence, and gains the primary sequence to output the primary feedback sequence. The data sampling circuit sequentially samples, according to the data clock, the primary sequence to output secondary sequences. The data sampling circuit gains the corresponding secondary sequences to output the secondary feedback sequences. The edge sampling circuit is configured to sequentially sample, according to an edge clock, the first added sequence to output an edge sequence.

An equalizer circuit includes a first arithmetic circuit, a second arithmetic circuit, a data sampling circuit, and an edge sampling circuit. The first arithmetic circuit is configured to compensate an equalization sequence by secondary feedback sequences to output a first added sequence. The second arithmetic circuit is configured to compensate the first added sequence by a primary feedback sequence to output a second added sequence. The data sampling circuit samples, according to data clock, the second added sequence to output a primary sequence, and gains the primary sequence to output the primary feedback sequence. The data sampling circuit sequentially samples, according to the data clock, the primary sequence to output secondary sequences. The data sampling circuit gains the corresponding secondary sequences to output the secondary feedback sequences. The edge sampling circuit is configured to sequentially sample, according to an edge clock, the first added sequence to output an edge sequence.

A transceiver architecture supports high-speed communication over a signal lane that extends between a high-performance integrated circuit (IC) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers. The architecture compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex transmit and receive equalization circuitry on the higher-performance side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated based upon the signal response at the receiver of the higher-performance IC.

An equalizer circuit includes a first arithmetic circuit, a second arithmetic circuit, a data sampling circuit, and an edge sampling circuit. The first arithmetic circuit is configured to compensate an equalization sequence by secondary feedback sequences to output a first added sequence. The second arithmetic circuit is configured to compensate the first added sequence by a primary feedback sequence to output a second added sequence. The data sampling circuit samples, according to data clock, the second added sequence to output a primary sequence, and gains the primary sequence to output the primary feedback sequence. The data sampling circuit sequentially samples, according to the data clock, the primary sequence to output secondary sequences. The data sampling circuit gains the corresponding secondary sequences to output the secondary feedback sequences. The edge sampling circuit is configured to sequentially sample, according to an edge clock, the first added sequence to output an edge sequence.

A transceiver architecture supports high-speed communication over a signal lane that extends between a high-performance integrated circuit (IC) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers. The architecture compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex transmit and receive equalization circuitry on the higher-performance side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated based upon the signal response at the receiver of the higher-performance IC.

Equalization circuitry for a data channel in an integrated circuit device includes an analog equalization stage coupled to the data channel, and a digital signal processing stage downstream of the analog equalization stage. The digital signal processing stage generates control signals to control the analog equalization stage, and includes a digital equalization stage that operates on output of the analog equalization stage. The analog equalization stage may further include an enhanced processing stage for optical signals, which may be selectably coupled to the analog equalization stage. The analog equalization stage may include at least one feed-forward or feedback equalization stage, and a decision stage that outputs decision signals at one of a first plurality of signal levels. The enhanced processing stage operates on the decision signals to output enhanced decision signals at one of a second plurality of signal levels of higher resolution than the first plurality of signal levels.

A memory interface may include a transmitter that generates multi-level signals. The transmitter may employ channel equalization to improve the quality and robustness of the multi-level signals. The channel equalization may be controlled independently from the drive strength of the multi-level signals. For example, a first control signal may control the de-emphasis or pre-emphasis applied to a multi-level signal and a second control signal may control the drive strength of the multi-level signal. The first control signal may control a channel equalization driver circuit and the second control signal may control a driver circuit.