The present invention is directed to communication methods and systems thereof. In a specific embodiment, a noise cancelation system includes a slicer that processes a data stream generates both PAM symbols and error data. An RIN estimator generates RIN data based on the PAM symbols and the error data. A filter removes non-RIN information from the RIN data. The filtered RIN data includes an offset term and a gain term, which are used to remove RIN noise from the data stream. There are other embodiments as well.

The invention provides an optical interconnect system and method for a data center. A nonlinear differential precoding module performs nonlinear differential precoding on an inputted original signal, to obtain a precoded signal with an increased quantity of levels. A generalized Tomlinson-Harashima precoding (GTHP) module pre-equalizes the precoded signal, to obtain a pre-equalized signal with scattered distribution. A faster than Nyquist (FTN) module performs high-frequency truncation filtering on the pre-equalized signal, to obtain a discrete signal. A signal transmission module transmits the discrete signal from a transmitting end to a receiving end. A feed-forward equalizer (FFE) performs strong equalization on the discrete signal to obtain a level slice signal, and decodes the level slice signal according to a GTHP decoding table, to obtain a decoded signal. A simplified 2D constellation distortion module processes the decoded signal to reshape a constellation, and obtains a restored signal according to a time interleaving method.

A receiver circuit includes a clock lane propagating a clock signal. A self-sampled clock applies a delayed version of the clock signal to the clock signal and compensation logic controls an amount of delay of the delayed version of the clock, based on a reference voltage offset (difference) between the receiver and a transmitter. The delayed version of the clock is centered on one unit interval of the clock. An offset correction is computed as a global offset value based on a clock duty cycle error, combined with a local offset value for each data lane, and is applied to data receiver front ends.

A receiver circuit includes a clock lane propagating a clock signal. A self-sampled clock applies a delayed version of the clock signal to the clock signal and compensation logic controls an amount of delay of the delayed version of the clock, based on a reference voltage offset (difference) between the receiver and a transmitter. The delayed version of the clock is centered on one unit interval of the clock. An offset correction is computed as a global offset value based on a clock duty cycle error, combined with a local offset value for each data lane, and is applied to data receiver front ends.

A receiver device implements enhanced data reception with edge-based clock and data recovery such as with a flash analog-to-digital converter architecture. In an example embodiment, the device implements a first phase adjustment control loop, with for example, a bang-bang phase detector, that detects data transitions for adjusting sampling at an optimal edge time with an edge sampler by adjusting a phase of an edge clock of the sampler. This loop may further adjust sampling in received data intervals for optimal data reception by adjusting the phase of a data clock of a data sampler such a flash ADC. The device may also implement a second phase adjustment control loop with, for example, a baud-rate phase detector, that detects data intervals for further adjusting sampling at an optimal data time with the data sampler.

The present invention is directed to communication methods and systems thereof. In a specific embodiment, a noise cancelation system includes a slicer that processes a data stream generates both PAM symbols and error data. An RIN estimator generates RIN data based on the PAM symbols and the error data. A filter removes non-RIN information from the RIN data. The filtered RIN data includes an offset term and a gain term, which are used to remove RIN noise from the data stream. There are other embodiments as well.

A system and method for efficiently transporting data in a computing system are contemplated. In various embodiments, a computing system includes a source, a destination and multiple lanes between them for transporting data. Multiple receivers in the destination has a respective termination resistor connected to a single integrating capacitor, which provides a reference voltage to the multiple receivers. The receivers reconstruct the received data by comparing the corresponding input signals to the reference voltage. The source includes a table storing code words. The source maps a generated data word to a code word, which is sent to the destination. The destination maps the received code word to the data word. The values of the code words are selected to maintain a nearly same number of Boolean ones on the multiple lanes over time as a number of Boolean zeroes.

A device includes a decoder configured to receive an input signal. The decoder is configured to also output a control signal based on the input signal. The device further includes an equalizer configured to receive a distorted bit as part of a data stream, receive the control signal, select a distortion correction factor based upon the control signal, apply the distortion correction factor to the distorted bit to offset inter-symbol interference from the data stream on the distorted input data to generate a modified value of the distorted bit, and generate a corrected bit based on the modified value of the distorted bit.

A system and method for efficiently transporting data in a computing system are contemplated. In various embodiments, a computing system includes a source, a destination and multiple lanes between them for transporting data. Multiple receivers in the destination has a respective termination resistor connected to a single integrating capacitor, which provides a reference voltage to the multiple receivers. The receivers reconstruct the received data by comparing the corresponding input signals to the reference voltage. The source includes a table storing code words. The source maps a generated data word to a code word, which is sent to the destination. The destination maps the received code word to the data word. The values of the code words are selected to maintain a nearly same number of Boolean ones on the multiple lanes over time as a number of Boolean zeroes.

A device includes a decoder configured to receive an input signal. The decoder is configured to also output a control signal based on the input signal. The device further includes an equalizer configured to receive a distorted bit as part of a data stream, receive the control signal, select a distortion correction factor based upon the control signal, apply the distortion correction factor to the distorted bit to offset inter-symbol interference from the data stream on the distorted input data to generate a modified value of the distorted bit, and generate a corrected bit based on the modified value of the distorted bit.