The encoding method includes an encoding process of encoding a bit sequence to be transmitted, into a symbol sequence. The symbol sequence includes a plurality of symbols each having a signal level to which any one of 2.sup.n different values is allocated. n is an integer equal to or larger than 1. The encoding process includes encoding the bit sequence to be transmitted into the symbol sequence so that the symbol sequence does not include one or more prohibited patterns. The one or more prohibited patterns include one or more specific patterns which are one or more of patterns representing transition of signal levels of three or more consecutive symbols. The one or more specific patterns include one or more patterns in which signal levels of any two adjacent symbols of the three or more consecutive symbols are different values.

Techniques are disclosed relating to DC interference cancelation in received wireless signals. Disclosed techniques may be performed in the digital domain, in conjunction with analog cancelation techniques. In some embodiments, a receiver apparatus operates a local oscillator at a frequency corresponding to a particular pilot symbol in a received wireless signal. In some embodiments the receiver estimates DC interference at the frequency based on the received pilot symbol (this may be facilitated by the fact that the contents of pilot symbols are known, because they are typically used for channel estimation). In some embodiments, the receiver apparatus is configured to cancel the DC interference based on the estimate to determine received data in subsequently received signals at the frequency. Disclosed techniques may allow narrowband receivers to efficiently use more of their allocated frequency bandwidth, rather than wasting bandwidth near the frequency of the local oscillator.

The card reader includes a peak detector that detects a peak point of a reproduced signal according to a threshold. The peak detector applies, to a first peak value to be determined, a second peak value immediately before the first peak value, a third peak value, which is the second preceding peak value with respect to the first peak value, and a next peak value. When a difference between a first intermediate value, which is a value between the third peak value and the second peak value, and a second intermediate value, which is a value between the second peak value and the first peak value, is greater than or equal to a first difference value, the peak detector ignores a first threshold, and decides the first peak value after confirming that a digital value corresponding to the next peak value has exceeded a second threshold.

A receiver device implements enhanced data reception with edge-based clock and data recovery such as with a flash analog-to-digital converter architecture. In an example embodiment, the device implements a first phase adjustment control loop, with for example, a bang-bang phase detector, that detects data transitions for adjusting sampling at an optimal edge time with an edge sampler by adjusting a phase of an edge clock of the sampler. This loop may further adjust sampling in received data intervals for optimal data reception by adjusting the phase of a data clock of a data sampler such a flash ADC. The device may also implement a second phase adjustment control loop with, for example, a baud-rate phase detector, that detects data intervals for further adjusting sampling at an optimal data time with the data sampler.

A peak detecting unit includes: a judging section, judging whether a current digital value produced by an AD converter has changed from a prior digital value; a holding section, being capable of holding the digital value output from the AD converter as an extreme value and its position information; and an updating section which, when the current digital value has changed from the prior digital value, updating the extreme value and its position information held in the holding section with the current digital value as a current extreme value and its position information, or when the current digital value matches the prior digital value, acquiring the intermediate position between the position of the current digital value and the position of the prior digital value as a current extreme value position, holding the matching digital value as a current extreme value, and updating the position information with the intermediate position information.

Techniques are disclosed relating to DC interference cancelation in received wireless signals. Disclosed techniques may be performed in the digital domain, in conjunction with analog cancelation techniques. In some embodiments, a receiver apparatus operates a local oscillator at a frequency corresponding to a particular pilot symbol in a received wireless signal. In some embodiments the receiver estimates DC interference at the frequency based on the received pilot symbol (this may be facilitated by the fact that the contents of pilot symbols are known, because they are typically used for channel estimation). In some embodiments, the receiver apparatus is configured to cancel the DC interference based on the estimate to determine received data in subsequently received signals at the frequency. Disclosed techniques may allow narrowband receivers to efficiently use more of their allocated frequency bandwidth, rather than wasting bandwidth near the frequency of the local oscillator.

A wireless power transfer device may include a circuit couplable with a coil to transmit or receive a first signal providing wireless power through the coil. The first signal may be modulated with second signals. A packet within any of the second signals may include first bits associated with a preamble and second bits associated with data. The device may further include a controller to measure temporal variations of at least one of the first signal, a rectified version of the first signal, or the one or more second signals. The controller may further determine thresholds for distinguishing between bits in the packet based on the temporal variations. The device may further demodulate the signals using the one or more thresholds to identify the preamble of the packet and extract the second bits associated with data from the packet when the preamble of the packet is identified.

A receiver device implements enhanced data reception with edge-based clock and data recovery such as with a flash analog-to-digital converter architecture. In an example embodiment, the device implements a first phase adjustment control loop, with for example, a bang-bang phase detector, that detects data transitions for adjusting sampling at an optimal edge time with an edge sampler by adjusting a phase of an edge clock of the sampler. This loop may further adjust sampling in received data intervals for optimal data reception by adjusting the phase of a data clock of a data sampler such a flash ADC. The device may also implement a second phase adjustment control loop with, for example, a baud-rate phase detector, that detects data intervals for further adjusting sampling at an optimal data time with the data sampler.

The card reader includes a peak detector that detects a peak point of a reproduced signal according to a threshold. The peak detector applies, to a first peak value to be determined, a second peak value immediately before the first peak value, a third peak value, which is the second preceding peak value with respect to the first peak value, and a next peak value. When a difference between a first intermediate value, which is a value between the third peak value and the second peak value, and a second intermediate value, which is a value between the second peak value and the first peak value, is greater than or equal to a first difference value, the peak detector ignores a first threshold, and decides the first peak value after confirming that a digital value corresponding to the next peak value has exceeded a second threshold.

A serial data receiver subsystem included in a computer system may include a data detection circuit, a speed detection circuit, and a receiver circuit that includes multiple subcircuits. The data detection circuit performs a comparison of a reference voltage to the magnitude of signals received via a communication link that encodes a serial data stream consisting of multiple data symbols. Using a result of the comparison, the data detection circuit may activate a signal present indicator indicating the presence of data on the communication link. Once the signal present indicator is active, the speed detection circuit checks the number of transitions to determine a rate at which data is being transmitted. In response to a determination that the rate of the data being transmitted exceeds a threshold value, the receiver circuit activates one or more of the multiple subcircuits.