A receiver includes a passive CTLE (continuous-time linear equalizer) configured to receive a first voltage signal from a first node and output a current signal to a second node in accordance with a first control signal; a CG (common-gate) amplifier configured to receive the current signal and output a second voltage signal at a third node in accordance with a second control signal; a first active inductor configured to provide an inductive load at the third node; a CS (common-source) CTLE configured to receive the second voltage signal and output a third voltage signal at a fourth node in accordance with a third control signal; a second active inductor configured to provide an inductive load at the fourth node; and a decision circuit configured to receive the third voltage signal and output a decision in accordance with a clock signal.

An electronic assembly including a plurality of electrically conductive elements separated by insulative material and a digital FM demodulator circuit coupled to some of the electrically conductive elements. The FM demodulator circuit having an FM detector circuit and a DC drift reducing circuit. The FM detector circuit has a detector input and a detector output that is the output of a comparator that is AC coupled to the rest of the FM detector circuit, the detector input receiving an input signal. The DC drift reducing circuit is electrically coupled to the detector output of the comparator, the DC drift reducing circuit detecting a DC drift of the detector output, the DC drift reducing circuit being additionally coupled to an input of the comparator, the DC drift reducing circuit substantially eliminating DC drift at the output of the FM demodulator circuit.

An EHF receiver that determines an initial slicing voltage level and dynamically adjusts the slicing voltage level and/or amplifier gain levels to account for characteristics of the received EHF electromagnetic data signal. The architecture includes an amplifier, detector, adaptive signal slicer, and controller. The detector includes a main detector and replica detector that convert the received EHF electromagnetic data signal into a baseband signal and a reference signal. The controller uses the baseband signal and reference signal to determine an initial slicing voltage level, and dynamically adjust the slicing voltage level and the gain settings of the amplifier to compensate for changing signal conditions.

Methods, apparatuses, and systems related to operations for measuring the quality of a signal received by a memory device and providing feedback. The memory device can sample signal data using a predetermined sequence of timing offsets relative to a reference signal. Additionally or alternatively, the memory device can sample the signal data using a predetermined sequence of reference voltages. The memory device can provide feedback results to a controller regarding the quality of the sampled signal data.

A method and system are provided for drift compensation, providing a live data approach to sampler offset calibration, such as for voltage and/or temperature (VT) drift. A serializer/deserializer (SerDes) system includes a SerDes receiver and receiver logic, the receiver logic including a forward error correction (FEC) module. A drift compensation device, or drift compensation engine, receives live error corrections from the FEC module based on FEC operations performed on live traffic passing through the SerDes receiver. A drift compensation command is provided to a data sampler in the SerDes receiver, to adjust a sampling voltage of the data sampler. When the system includes a plurality of data samplers, the drift compensation device determines the data sampler with which an error correction is associated. The drift compensation command can be sent after a threshold criterion is satisfied, such as completion of a statistics collection period, or a threshold number of corrections.

A reference generator for use with serial link data communication is disclosed. Broadly speaking, a decision circuit may perform a comparison between a particular data symbol included in a serial data stream and a difference between a voltage level of a first signal and a voltage level of a second signal, and generate an output data value based on a result of the comparison. A reference generator circuit may selectively sink a first current value from either the first signal or the second signal based upon another output data value generated from another data symbol included in the serial data stream that was received prior to the particular data symbol.

An example of an isolation sensor package is disclosed to include a first Integrated Circuit (IC) chip and a second IC chip. The first IC chip may include an input interface circuit that receives an input signal from a first input signal terminal and a second input signal terminal, where the input signal ranges between a first positive voltage and a first negative voltage. The first IC chip may further include a negative voltage generator that generates a second negative voltage, a level shifter that receives an output of the input interface circuit and generates a modified signal having a voltage level between a ground voltage provided to the ground terminal and a second positive voltage that is present at a voltage supply terminal. The first IC chip may further produce a signal based on the modified signal generated by the level shifter.

A signaling system is described. The signaling system comprises a transmit device, a receive device including a partial response receive circuit, and a signaling path coupling the transmit device and the receive device. The receive device observes an equalized signal from the signaling path, and includes circuitry to use feedback from the most recent previously resolved symbol to sample a currently incoming symbol. The transmit device equalizes transmit data to transmit the equalized signal, by applying weighting based on one or more data values not associated with the most recent previously resolved symbol value.

A receiver includes: an automatic gain controller (AGC) configured to receive an analog signal; an analog-to-digital converter (ADC) configured to receive an output from the AGC and to output a digitized signal, wherein a most significant bit of the digitized signal corresponds to a sliced data, and a least significant bit of the digitized signal corresponds to an error signal; and an adaptation unit configured to control the AGC, the ADC, or both the AGC and the ADC, based at least in part on the digitized signal to achieve a desired data digitization and data slicing.

A reference generator for use with serial link data communication is disclosed. Broadly speaking, a decision circuit may perform a comparison between a particular data symbol included in a serial data stream and a difference between a voltage level of a first signal and a voltage level of a second signal, and generate an output data value based on a result of the comparison. A reference generator circuit may selectively sink a first current value from either the first signal or the second signal based upon another output data value generated from another data symbol included in the serial data stream that was to received prior to the particular data symbol.