Generating a composite interpolated phase-error signal for clock phase adjustment of a local oscillator by forming a summation of weighted phase-error signals generated using a matrix of partial phase comparators, each of which compare a phase of the local oscillator with a corresponding phase of a reference clock.

An encoder for modulating data on level transitions of a signal transmitted on a wired communication channel to increase channel data throughput, comprising a circuitry configured for receiving a signal transmitted by a transmitting communication node, the signal carries a message to one or more receiving communication nodes connected to a wired communication channel, calculating a respective delay period consisting of a number of delay time units encoding one or more data items, delaying one or more transitions of a waveform level of the signal by the respective delay period to modulate the signal to carry the data item(s) and transmitting the modulated signal to one or more of the receiving communication nodes having a decoder configured for demodulating the modulated signal.

An encoder for modulating data on level transitions of a signal transmitted on a wired communication channel to increase channel data throughput, comprising a circuitry configured for receiving a signal transmitted by a transmitting communication node, the signal carries a message to one or more receiving communication nodes connected to a wired communication channel, calculating a respective delay period consisting of a number of delay time units encoding one or more data items, delaying one or more transitions of a waveform level of the signal by the respective delay period to modulate the signal to carry the data item(s) and transmitting the modulated signal to one or more of the receiving communication nodes having a decoder configured for demodulating the modulated signal.

A differential signal processing device is described which includes an encoder configured to encode input data into one or more differential signals and a transmitter configured to sequentially transmit the one or more differential signals using a plurality of transmission lines. The encoder converts a plurality of bits, corresponding to a transmission time interval, among the input data into an encoding code array in the transmission time interval obtained by increasing an encoding unit time, encoded for each of the one or more differential signals, by an integer multiple.

A differential signal processing device is described which includes an encoder configured to encode input data into one or more differential signals and a transmitter configured to sequentially transmit the one or more differential signals using a plurality of transmission lines. The encoder converts a plurality of bits, corresponding to a transmission time interval, among the input data into an encoding code array in the transmission time interval obtained by increasing an encoding unit time, encoded for each of the one or more differential signals, by an integer multiple.

A receiver is configured to receive a series of command signals and a series of data signals. The receiver includes a first clock and data recovery (CDR) circuit, a control circuit and a second CDR circuit. The first CDR circuit is configured to process the series of command signal to generate a clock signal. The control circuit, coupled to the first CDR circuit, is configured to generate a control signal according to the series of command signals and the clock signal received from the first CDR circuit. The second CDR circuit, coupled to the control circuit, is configured to process the series of data signals according to the control signal received from the control circuit.

Embodiments of a method and a device are disclosed. In an embodiment, a method for operating a wired communications device involves including a frame boundary bit sequence and a random data sequence as a preamble of a bit stream, encoding the bit stream into an encoded bit stream, and transmitting the encoded bit stream using the wired communications device.

Embodiments of a method and a device are disclosed. In an embodiment, a method for operating a wired communications device involves performing a bit mapping operation on an input bit stream to generate a mapped bit stream, performing a bit scrambling operation in response to the mapped bit stream to generate a scrambled bit stream, generating an encoded bit stream in response to the scrambled bit stream, and transmitting the encoded bit stream using the wired communications device.

Generating a composite interpolated phase-error signal for clock phase adjustment of a local oscillator by forming a summation of weighted phase-error signals generated using a matrix of partial phase comparators, each of which compare a phase of the local oscillator with a corresponding phase of a reference clock.

Generating a composite interpolated phase-error signal for clock phase adjustment of a local oscillator by forming a summation of weighted phase-error signals generated using a matrix of partial phase comparators, each of which compare a phase of the local oscillator with a corresponding phase of a reference clock.