This disclosure provides a clock recovery circuit for a multi-lane communication system. Local clocks are recovered from the input signals using respective local CDR circuits, and associated CDR error signals are aggregated or otherwise combined. A global recovered clock for shared use by the local CDR circuits is generated at a controllable oscillation frequency as a function of a combination of the error signals from the plurality of receivers. A voltage- or current-controlled delay line can also be used to phase adjust the global recovered clock to mitigate band-limited, lane-correlated, high frequency jitter.

This disclosure provides a clock recovery circuit for a multi-lane communication system. Local clocks are recovered from the input signals using respective local CDR circuits, and associated CDR error signals are aggregated or otherwise combined. A global recovered clock for shared use by the local CDR circuits is generated at a controllable oscillation frequency as a function of a combination of the error signals from the plurality of receivers. A voltage- or current-controlled delay line can also be used to phase adjust the global recovered clock to mitigate band-limited, lane-correlated, high frequency jitter.

A clock data recovery circuit includes; a clock recovery circuit that receives a pseudo random binary sequence (PRBS) pattern and generates a recovery clock by counting edges of the PRBS pattern, and a data recovery circuit that generates recovery data from at least one of the PRBS pattern and externally provided serial data.

Probabilistic shaping quadrature amplitude modulation (QAM) based on Maxwell-Boltzmann distribution is particularly important in coherent optical communication, which can approach the Shannon limit more desirably in the case of a finite signal-to-noise ratio. However, standard coherent optical digital signal processing algorithms are not optimal for demodulation of PS higher-order QAM signals. The invention provides a probabilistic shaping QAM dynamic equalization method that intercepts multiple inner rings after clock recovery and updates the convergence radius and area of a conventional blind dynamic channel equalization algorithm using a peak density K-means clustering algorithm. The clustering algorithm gives centroid labels and a quantity of classifications required for K-means, which does not require a large number of iterations of K-means, thereby reducing the complexity and improving the accuracy. The updated decision area and decision radius reduce errors in the dynamic equalization algorithm, thereby improving the accuracy of probabilistic shaping QAM digital signal processing.

Various techniques are provided to efficiently implement user designs incorporating clock and/or data recovery circuitry and/or a deserializer in programmable logic devices (PLDs). In one example, a method includes receiving a serial data stream, measuring time periods between signal transitions in a serial data stream using at least one Grey code oscillator, and generating a recovered data signal corresponding to the serial data stream by, at least in part, comparing the measured time periods to one or more calibration time periods. In another example, a system includes a Grey code oscillator configured to increment a Grey code count between signal transitions in a serial data stream, and a Grey code converter configured to convert the Grey code count approximately at the signal transitions to a plurality of binary counts each corresponding to a time period between one or more signal transitions in the serial data stream.

This invention discloses a multicarrier communication system that includes a transmitter equipment and a receiver equipment. According to a timing scheme, the transmitter equipment processes multiple original symbols for transmission on multiple subcarrier channels, and the receiver equipment processes and detects multiple received symbols from the multiple subcarrier channels. During a time frame of data transmission, the initial three of the original symbols for each of the subcarrier channels are three pilot symbols, forming a preamble. The three preambles of every consecutive three of the subcarrier channels form a preamble unit. All the pilot symbols of the preamble unit are expressed as a 33 matrix. When the center pilot symbol of the preamble unit is normalized to 1 or j (i.e., the imaginary unit), the matrix is $\left[\begin{array}{ccc}-j& -j& -j\\ j& 1& -j\\ -j& j& -j\end{array}\right]\mathrm{or}[\begin{array}{ccc}1& 1& 1\\ -1& j& 1\\ 1& -1& 1\end{array}$

This disclosure provides a clock recovery circuit for a multi-lane communication system. Local clocks are recovered from the input signals using respective local CDR circuits, and associated CDR error signals are aggregated or otherwise combined. A global recovered clock for shared use by the local CDR circuits is generated at a controllable oscillation frequency as a function of a combination of the error signals from the plurality of receivers. A voltage- or current-controlled delay line can also be used to phase adjust the global recovered clock to mitigate band-limited, lane-correlated, high frequency jitter.

This invention discloses a multicarrier communication system that includes a transmitter equipment and a receiver equipment. According to a timing scheme, the transmitter equipment processes multiple original symbols for transmission on multiple subcarrier channels, and the receiver equipment processes and detects multiple received symbols from the multiple subcarrier channels. During a time frame of data transmission, the initial three of the original symbols for each of the subcarrier channels are three pilot symbols, forming a preamble. The three preambles of every consecutive three of the subcarrier channels form a preamble unit. All the pilot symbols of the preamble unit are expressed as a 33 matrix. When the center pilot symbol of the preamble unit is normalized to 1 or j (i.e., the imaginary unit), the matrix is

[00001]$\left[\begin{array}{ccc}-j& -j& -j\\ j& 1& -j\\ -j& j& -j\end{array}\right].Math..Math.\mathrm{or}.Math.\left[\begin{array}{ccc}1& 1& 1\\ -1& j& 1\\ 1& -1& 1\end{array}\right].$

A channel estimation method for the multicarrier communication system is also disclosed.

An anti-aliasing channel estimation apparatus and method and a receiver where the anti-aliasing channel estimation method includes: performing clock recovery and data synchronization on a received multicarrier signal with channel aliasing, to obtain a synchronized time-domain signal and a sampling phase; calculating an estimation signal after passing through a channel and being aliased based on a training sequence and the sampling phase, and obtaining a channel response and an aliasing signal response of each subcarrier of the multicarrier signal based on the estimation signal and the frequency-domain signal. Therefore, channel estimation may be performed on the multicarrier signal with channel aliasing, influence of the channel aliasing on the bit error rate may be lowered, and transmission quality of the system may be improved.

A method for operating an RFID device is disclosed. In the embodiment, the method involves establishing a radio-frequency link, receiving signal samples of the radio-frequency link, determining the offset of an initial phase of the link by filtering noise from the signal samples, windowing the filtered signal samples, and calculating an offset value from phase differences between the windows of signal samples, and modifying a configuration profile based on the offset value. During data transmission the configuration profile can be used to configure the transmitter in order to maintain the constant phase during transmission.