A carrier generator includes a phase accumulator configured to generate a phase reference signal based on a frequency command word (FCW) signal, a time to digital converter (TDC) configured to generate a feedback signal based on a divided signal, a loop filter configured to generate a filtered command signal based on the phase reference signal and the feedback signal, and a plurality of tuning arrangements. Each tuning arrangement includes an oscillator configured to receive the filtered command signal and output an adjustment signal, and is configured to output a carrier signal of a corresponding plurality of carrier signals based on the adjustment signal. The divided signal is based on the adjustment signal of a first tuning arrangement.

Various techniques are provided to efficiently implement user designs incorporating clock and/or data recovery circuitry and/or a deserializer in programmable logic devices (PLDs). In one example, a method includes receiving a serial data stream, measuring time periods between signal transitions in a serial data stream using at least one Grey code oscillator, and generating a recovered data signal corresponding to the serial data stream by, at least in part, comparing the measured time periods to one or more calibration time periods. In another example, a system includes a Grey code oscillator configured to increment a Grey code count between signal transitions in a serial data stream, and a Grey code converter configured to convert the Grey code count approximately at the signal transitions to a plurality of binary counts each corresponding to a time period between one or more signal transitions in the serial data stream.

Various techniques are provided to efficiently implement user designs incorporating clock and/or data recovery circuitry and/or a deserializer in programmable logic devices (PLDs). In one example, a method includes receiving a serial data stream, measuring time periods between signal transitions in a serial data stream using at least one Grey code oscillator, and generating a recovered data signal corresponding to the serial data stream by, at least in part, comparing the measured time periods to one or more calibration time periods. In another example, a system includes a Grey code oscillator configured to increment a Grey code count between signal transitions in a serial data stream, and a Grey code converter configured to convert the Grey code count approximately at the signal transitions to a plurality of binary counts each corresponding to a time period between one or more signal transitions in the serial data stream.

A communication system includes a first radio module and a second radio module. The first radio module includes a tuner communicatively coupled to a reference signal generator that is configured to generate a first reference signal for the tuner. The first radio module further includes a serializer configured to serialize a signal output by the tuner. The second radio module includes a deserializer configured to receive a serialized version of the signal from the serializer of the first radio module and deserialize the serialized version of the signal. The second radio module further includes a second tuner that is communicatively coupled to a clock recovery circuit. The clock recovery circuit is configured to generate a second reference signal for the second tuner based on a deserialized version of the first signal, where the second reference signal is frequency and phase locked to the first reference signal.

This disclosure provides a clock recovery circuit for a multi-lane communication system. Local clocks are recovered from the input signals using respective local CDR circuits, and associated CDR error signals are aggregated or otherwise combined. A global recovered clock for shared use by the local CDR circuits is generated at a controllable oscillation frequency as a function of a combination of the error signals from the plurality of receivers. A voltage- or current-controlled delay line can also be used to phase adjust the global recovered clock to mitigate band-limited, lane-correlated, high frequency jitter.

A clock data recovery circuit includes; a clock recovery circuit that receives a pseudo random binary sequence (PRBS) pattern and generates a recovery clock by counting edges of the PRBS pattern, and a data recovery circuit that generates recovery data from at least one of the PRBS pattern and externally provided serial data.

An embodiment of the present invention relates to an ultra low power wideband asynchronous binary phase shift keying (BPSK) demodulation method and a circuit configuration thereof. The ultra low power wideband asynchronous BPSK demodulation circuit comprises a sideband division and upper sideband signal delay unit dividing a modulated signal into an upper sideband and a lower sideband by a first order high-pass filter and a first order low-pass filter; a data demodulation unit latching, through a hysteresis circuit, a signal generated by a difference between the analog signals in which a phase difference between the delayed upper sideband analog signal and the lower sideband analog signal is aligned at 0, so as to demodulate digital data; and a data clock recovery unit for generating a data clock by using a signal digitalized from the lower sideband analog signal through a comparator and a data signal.

A RXLOS deglitch apparatus for a receiver is provided. The RXLOS deglitch apparatus includes a sampler, an edge detecting unit and a finite state machine. The sampler receives a recovered clock, and samples a RXLOS signal according to the recovered clock. Consequently, a sampled RXLOS signal is generated. The edge detecting unit receives the RXLOS signal. When a logic level of the RXLOS signal is changed, an edge detection signal is activated by the edge detecting unit. The finite state machine receives the edge detection signal and the sampled RXLOS signal, generates an edge rest signal to control the edge detecting unit, and outputs a filtered RXLOS signal.

In an embodiment, a circuit includes a synchronizer configured to generate a trigger signal synchronized to a reference clock. A synthesizer is configured to synthesize a signal according to frequency control data in response to the trigger signal. A radio receiver is configured to process a carrier signal according to the synthesized signal. A phase measurement unit is configured to measure a first channel frequency response based on the processed carrier signal.

This disclosure provides a clock recovery circuit for a multi-lane communication system. Local clocks are recovered from the input signals using respective local CDR circuits, and associated CDR error signals are aggregated or otherwise combined. A global recovered clock for shared use by the local CDR circuits is generated at a controllable oscillation frequency as a function of a combination of the error signals from the plurality of receivers. A voltage- or current-controlled delay line can also be used to phase adjust the global recovered clock to mitigate band-limited, lane-correlated, high frequency jitter.