This disclosure provides a clock recovery circuit for a multi-lane communication system. Local clocks are recovered from the input signals using respective local CDR circuits, and associated CDR error signals are aggregated or otherwise combined. A global recovered clock for shared use by the local CDR circuits is generated at a controllable oscillation frequency as a function of a combination of the error signals from the plurality of receivers. A voltage- or current-controlled delay line can also be used to phase adjust the global recovered clock to mitigate band-limited, lane-correlated, high frequency jitter.

A wireless communication device includes: controlling circuitry configured to selectively switch an operating channel between a first channel and a second channel; and a transmitter configured to transmit a first beacon signal through the first channel at a first cycle and transmit a second beacon signal through the second channel at a second cycle. A first period during which transmission/reception of a signal is possible and a second period during which transmission/reception of a signal is not performed are set for the second channel within a transmission interval of second beacon signals. The controlling circuitry switches the operating channel from the second channel to the first channel during the second period. The transmitter transmits the first beacon signal through the first channel during the second period. The controlling circuitry switches the operating channel from the first channel to the second channel by an end of the second period.

A group of data symbols for a current block of data symbols in multiple blocks received over a communication channel is equalized, based on a pilot block, to generate a group of equalized symbols. The group of equalized symbols is de-rotated as a function of a current phase estimate to determine initial de-rotated equalized symbols. The phase estimate is an estimate of phase caused by noise for blocks previous to the current block. Additionally, a phase metric is calculated from real and imaginary parts of the initial de-rotated equalized symbols, wherein the phase metric estimates phase caused by noise for the current block. The current phase estimate is updated with the phase metric. The initial de-rotated equalized symbols are de-rotated by the phase metric to determine final equalized and de-rotated symbol estimates. The final equalized and de-rotated symbol estimates are output. Apparatus, methods, and computer program products are disclosed.

A phase calibration method for a phase locked loop (PLL) circuit in a wireless communication device includes: calculating a header phase error of a header sub-frame of a frame in an input signal and a pilot phase error of a pilot sub-frame of the frame, wherein the header sub-frame and the pilot sub-frame are known data; generating an estimated phase error according to a relationship between the header phase error and the pilot phase error; generating a phase compensating signal according to the estimated phase error and a filtered signal; adjusting the input signal according to the phase compensating signal to generate a compensated input signal; detecting a phase error between a data sub-frame corresponding to the pilot sub-frame in the compensated input signal and a reference signal; and generating the filtered signal according to the phase error.

Calibrating a Gaussian frequency-shift keying modulation index includes generating a training sequence of bits, shaping a pulse from the training sequence according to an initial modulation index, and converting the shaped signal to a transmission signal. The transmission signal is then either looped through a radio frequency core or processed by frequency deviation estimation hardware to determine a frequency deviation. The frequency deviation is converted to a new modulation index, and potentially a ratio between a target modulation index and a measured modulation index as a scaling factor. The process is then iteratively repeated until a threshold frequency deviation is achieved.

An I/Q imbalance calibration method includes sequentially inputting a first in-phase and quadrature signals calibration signal to a front-end circuit of the transmitter system to acquire and estimate a first and second calibration signal strengths sequentially, wherein a delta estimation is adopted; calculating an I/Q gain imbalance according to estimated first and second calibration signal strengths; sequentially inputting a second in-phase calibration signal and both of the second in-phase and quadrature calibration signal to the front-end circuit of the transmitter system to acquire and estimate a third and fourth calibration signal strengths sequentially, wherein an I/Q gain imbalance compensation is formed on the first in-phase and quadrature calibration signals to generate the second in-phase and quadrature calibration signals; and calculating an I/Q phase imbalance according to estimated third and fourth calibration signal strengths.

Various methods provide for trimming the gain in a dual-port phase-locked loop (PLL) of a radio transceiver. Use is made of the radio's demodulator to perform modulation accuracy measurements, thereby reducing the cost and complexity of external test equipment.

This disclosure provides a clock recovery circuit for a multi-lane communication system. Local clocks are recovered from the input signals using respective local CDR circuits, and associated CDR error signals are aggregated or otherwise combined. A global recovered clock for shared use by the local CDR circuits is generated at a controllable oscillation frequency as a function of a combination of the error signals from the plurality of receivers. A voltage- or current-controlled delay line can also be used to phase adjust the global recovered clock to mitigate band-limited, lane-correlated, high frequency jitter.

An automatic frequency control (AFC) device is provided. The AFC device includes an input module, a received signal strength indicator (RSSI) module and a carrier frequency offset (CFO) estimation module. The input module down converts and samples a received signal. The RSSI module is coupled to the input module and calculates a RSSI signal in response to the down converted and sampled received signal. The CFO estimation module is coupled to the input module and the RSSI module and calculates a moving average of binary elements of the down converted and sampled received signal. The CFO estimation module continues to calculate the moving average until the AFC converges.

A technique that reduces or eliminates trading-off power amplifier efficiency and costly external filtering in amplitude and phase modulated sinusoidal signal generation uses multi-phase outphasing and a multi-phase switching mode power amplifier to generate the amplitude and phase modulated sinusoidal signals. The technique combines multiple clock phases with sinusoidally weighted circuits of the switching mode power amplifier to improve amplitude and phase modulated sinusoidal signal generation.