Patent classifications
H04L2027/0055
Clock and data recovery having shared clock generator
This disclosure provides a clock recovery circuit for a multi-lane communication system. Local clocks are recovered from the input signals using respective local CDR circuits, and associated CDR error signals are aggregated or otherwise combined. A global recovered clock for shared use by the local CDR circuits is generated at a controllable oscillation frequency as a function of a combination of the error signals from the plurality of receivers. A voltage- or current-controlled delay line can also be used to phase adjust the global recovered clock to mitigate band-limited, lane-correlated, high frequency jitter.
SYSTEM AND METHOD FOR ENHANCED CHANNEL ESTIMATION USING TAP-DEPENDENT FREQUENCY OFFSET (FO) ESTIMATION
Apparatuses (and methods of manufacturing same), systems, and methods for channel interpolation/estimation and/or frequency tracking suitable for a receiver in a high speed single frequency network (HS-SFN) scenario are described. In one aspect, an estimated frequency offset (FO) correction is calculated for a received signal using at least an FO estimation provided by an automatic frequency control (AFC) in a first feedback loop and a channel estimate is calculated using at least the estimated FO and one or more channel parameter estimates from the AFC in a second feedback loop. In another aspect, a phase locked loop (PLL) receives an lth orthogonal frequency division multiplexing (OFDM) symbol and produces a per-tap phase value for each tap i of the lth OFDM symbol. The per-tap phase values of the lth OFDM symbol are used to generate the PLL output, which is also used as input to a feedback loop.
TRIM FOR DUAL-PORT FREQUENCY MODULATION
Various methods provide for trimming the gain in a dual-port phase-locked loop (PLL) of a radio transceiver. Use is made of the radio's demodulator to perform modulation accuracy measurements, thereby reducing the cost and complexity of external test equipment.
TRANSCEIVER USING TECHNIQUE FOR IMPROVEMENT OF PHASE NOISE AND SWITCHING OF PHASE LOCK LOOP (PLL)
A transceiver may include a reception (Rx) radio frequency (RF) part configured to process a received signal, a transmission (Tx) RF part configured to process a transmitted signal, and a phase lock loop (PLL) configured to provide a reception frequency to the reception RF part and provide a transmission frequency to the transmission RF part. The PLL may be controlled according to whether the reception RF part or the transmission RF part is on. In addition, a transceiver may include quenching waveform generator (QWGs) to control quenching waveforms of the RF parts corresponding to a plurality of antennas. The quenching waveforms may be generated respectively by VCOs operating at a same frequency. The QWGs may control the VCOs such that the quenching waveforms do not overlap.
Carrier synchronization appropriate for ALM NFC data transmission
In some aspects, the disclosure is directed to methods and systems for carrier synchronization in active load modulation for near field communications. A broadcast carrier is received from a remote device and mixed with a locally-generated carrier and modulated data. A carrier synchronization circuit synchronizes the locally-generated carrier with the broadcast carrier based on an identified phase error from a double Cartesian-to-polar mapping of the mixed locally-generated carrier and broadcast carrier. In some implementations, the system also includes a modulation suppression circuit for providing unmodulated carrier signals to the carrier synchronization circuit or suppressing modulation distortion to maintain frequency and phase tracking despite the presence of data.
RF RECEIVER WITH FREQUENCY TRACKING
A robust frequency drift tracking receiver. The received signal is translated to an intermediate frequency in the RF stage by a quadrature demodulator, and is then brought into the base band by a digital mixer made by a CORDIC. A base band processing, stage allows for a synchronisation of the receiver relative to the data frame, to estimate data and to output a counter-reaction signal to the CORDIC, obtained by integration of successive frequency corrections with a predetermined step.
Highly linear-gain oscillator
A variable frequency oscillator includes an inductance unit having a first inductance, a first variable capacitor coupled across the inductance unit, and a second variable capacitor coupled across a part of the inductance unit. The inductance of the part of the inductance unit coupled by the second variable capacitor is a proportion of the first inductance.
Automatic frequency control
An automatic frequency control device, a method for automatic frequency control, a receiver, a mobile station and a non-transitory computer-readable digital storage medium are provided. The automatic frequency control device may include a quality calculation unit to calculate quality of a received signal, a state machine controller to generate a control signal based on the calculated quality of the received signal, and a filter to filter an estimated frequency offset of the received signal based on the control signal.
Clock and Data Recovery Having Shared Clock Generator
This disclosure provides a clock recovery circuit for a multi-lane communication system. Local clocks are recovered from the input signals using respective local CDR circuits, and associated CDR error signals are aggregated or otherwise combined. A global recovered clock for shared use by the local CDR circuits is generated at a controllable oscillation frequency as a function of a combination of the error signals from the plurality of receivers. A voltage- or current-controlled delay line can also be used to phase adjust the global recovered clock to mitigate band-limited, lane-correlated, high frequency jitter.
Transceiver using technique for improvement of phase noise and switching of phase lock loop (PLL)
A transceiver may include a reception (Rx) radio frequency (RF) part configured to process a received signal, a transmission (Tx) RF part configured to process a transmitted signal, and a phase lock loop (PLL) configured to provide a reception frequency to the reception RF part and provide a transmission frequency to the transmission RF part. The PLL may be controlled according to whether the reception RF part or the transmission RF part is on. In addition, a transceiver may include quenching waveform generator (QWGs) to control quenching waveforms of the RF parts corresponding to a plurality of antennas. The quenching waveforms may be generated respectively by VCOs operating at a same frequency. The QWGs may control the VCOs such that the quenching waveforms do not overlap.