A phase locked loop circuit that is capable of stabilizing a frequency of an input signal even in the case where the frequency is unstable is provided. The phase locked loop circuit that corrects a frequency error of an output signal from an oscillator to a predetermined target frequency; an ADC that converts the output signal to a digital signal; reference frequency output means that outputs a reference frequency signal; frequency error detection means that detects the frequency error based on the digital signal and the reference frequency signal; correction signal generation means that generates an error correction signal based on the frequency error; a DAC that converts the error correction signal to an analog signal; and a multiplier that multiplies the output signal by the analog signal to correct the frequency error of the output signal.

An automatic frequency control (AFC) device is provided. The AFC device includes an input module, a received signal strength indicator (RSSI) module and a carrier frequency offset (CFO) estimation module. The input module down converts and samples a received signal. The RSSI module is coupled to the input module and calculates a RSSI signal in response to the down converted and sampled received signal. The CFO estimation module is coupled to the input module and the RSSI module and calculates a moving average of binary elements of the down converted and sampled received signal. The CFO estimation module continues to calculate the moving average until the AFC converges.

Automatic frequency controllers, automatic frequency control methods, wireless communication devices, and/or wireless communication methods are provided. The automatic frequency controllers for correcting a frequency offset between a base station and a terminal includes at least one processor communicatively coupled to a memory and configured to execute computer-readable instructions stored in the memory to obtain a phase estimate from a reference signal received from the base station; classify a downlink channel as a High Speed Train (HST) channel or a non-HST channel based on the phase estimate; adjust a loop gain according to the classified downlink channel; calculate a phase error based on the phase estimate and the loop gain; correct the frequency offset using the phase error; and communicate with the base station after correcting the frequency offset.

Methods and systems for correcting carrier frequency offsets (CFOs) in a wireless transceiver are disclosed. The method includes receiving a first predetermined number of data packets and analyzing the first predetermined number of data packets to determine one or more wireless link quality metrics. The method includes adjusting a local oscillator in accordance with a first local oscillator adjustment strategy. The method includes receiving a second predetermined number of data packets and analyzing the second predetermined number of data packets to determine the one or more wireless link quality metrics. The method includes repeating the first local oscillator adjustment strategy if the wireless link quality metrics improve. The method includes changing to a second local oscillator adjustment strategy if the wireless link quality metrics worsen and adjusting the local oscillator in accordance with the second local oscillator adjustment strategy.

A robust frequency drift tracking receiver. The received signal is translated to an intermediate frequency in the RF stage by a quadrature demodulator, and is then brought into the base band by a digital mixer made by a CORDIC. A base band processing stage allows for a synchronization of the receiver relative to the data frame, to estimate data and to output a counter-reaction signal to the CORDIC, obtained by integration of successive frequency corrections, with a predetermined step.

A receiver detects a received signal, transmitted by a transmitter to carry payload data as Orthogonal Frequency Division Multiplexed (OFDM) symbols in divided frames, each frame including a preamble including plural bootstrap OFDM symbols. A detector circuit detects, from the bootstrap OFDM symbols, a synchronization timing for converting a useful part of the bootstrap OFDM symbols into the frequency domain. A bootstrap processor detects an estimate of the channel transfer function from a first OFDM symbol, and a demodulator circuit recovers the signaling data from the bootstrap OFDM symbols using the estimate. The bootstrap processor includes an up-sampler configured to receive the bootstrap OFDM symbols, to form an up-sampled frequency domain version of the bootstrap OFDM symbol, and an output processor configured to identify a peak correlation result, to determine frequency offset of the received signal from a relative position of the peak correlation result in the frequency domain.

Described herein are systems and methods for accurately estimating and removing a carrier frequency offset. One exemplary embodiment relates to a system comprising a frequency offset detection circuit detecting a carrier frequency offset in an optical signal, and a frequency testing circuit calculating an estimated frequency offset value of the carrier frequency offset, wherein the frequency testing circuit removes a carrier phase based on the estimated frequency offset value and recovers the optical signal. Another exemplary embodiment relates to a method comprising detecting a carrier frequency offset in an optical signal, calculating an estimated frequency offset value of the carrier frequency offset, removing a carrier phase based on the estimated frequency offset value, and recovering the optical signal.

A radio transmitter (4) comprises an encoder (5) that receives one or more variable message bits, and encodes each message bit that has a first value as a predetermined first binary chip sequence and encodes each message bit that has the opposite value as a predetermined second binary chip sequence. The radio transmitter (4) transmits data packets, each comprising (i) a predetermined synchronization portion, comprising one or more instances of the first binary chip sequence, and (ii) a variable data portion, comprising one or more encoded message bits output by the encoder. A radio receiver (9) receives such data packets. It uses the synchronization portion of a received data packet to perform a frequency and/or timing synchronization operation, and then decodes message bits from the data portion of the data packet.

A method for frequency and time synchronization with respect to a satellite, the method including: calculating a frequency offset ({circumflex over (f)}.sub.B,e) due to an instability of a satellite oscillator from a beacon signal (f.sub.B,TX.sup.N); determining a Satellite Motion Doppler Correction for Ephemeris (SMDC.sub.e) of a satellite motion based on ephemeris data for the satellite; computing a Satellite Reference Drift Correction for Ephemeris (SRDC.sub.e) based on the frequency offset, the beacon signal and the SMDC.sub.e; setting a loopback TX frequency based on the SMDC.sub.e and the SRDC.sub.e; and transmitting a loopback TX signal to the satellite at the loopback TX frequency.

Processing a digital bit stream and systems for implementing the methods are provided. The method includes dividing the digital bit stream into a plurality of data packets. In a first processing block performing a carrier recovery error calculation on a first portion of the plurality of data packets, comprising preforming a first phase locked loop (PLL) function on decimated data of the data packets and performing a carrier recovery operation on the first portion of the plurality of data packets. In a second processing block, in parallel with the processing of the first portion of the plurality of packets, performing the carrier recovery error calculation on a second portion of the plurality of data packets, comprising preforming the first PLL function on decimated data of the data packets and performing the carrier recovery operation on second portion of the plurality of data packets.