Disclosed are systems, methods, and structures for DSP-free coherent receiver architectures applicable for short-reach optical links. Operationally, a received optical signal is down-converted by mixing it with a local oscillator (LO) laser signal using a 90-degree hybrid followed by balanced photodiodes. Other receiver functions are performed using analog signal processing thereby avoiding power-hungry, high-speed analog-to-digital converters and high-speed digital signal processing. Carrier phase recovery is performed by an electrical phase-locked loop employing a multiplier-free phase estimator stage thatwhile designed for quaternary phase-shift keying signalsmay be employed in designs exhibiting higher modulation formats. Since carrier phase recovery is performed in the electrical domain, LO laser frequency modulation or LO laser integration is not employed. Polarization demultiplexingif employedmay be performed by the addition of an optical polarization controller prior to the hybrid and may advantageously be realized by cascading multiple phase shifters driven by low-speed circuitry.

Disclosed are an IQ mismatch compensation method and apparatus for a radio frequency communication system, a compensation device and a communication device. The method comprises: acquiring an interaction result of test signals between a transmitting component and a receiving component; obtaining angle mismatch parameters of a pre-determined type according to the interaction result; determining a frequency domain compensator for performing mismatch compensation on the frequency-dependent angle mismatch parameters according to the following formulae: Y(w)=X(w)jP(w)*X*(w) and Y(w)=X(w)+jP(w)*X*(w); and performing frequency domain compensation on the frequency-dependent angle mismatch parameters by using the frequency domain compensator. Also disclosed is a computer storage medium.

A receiver device implements enhanced data reception with edge-based clock and data recovery such as with a flash analog-to-digital converter architecture. In an example embodiment, the device implements a first phase adjustment control loop, with for example, a bang-bang phase detector, that detects data transitions for adjusting sampling at an optimal edge time with an edge sampler by adjusting a phase of an edge clock of the sampler. This loop may further adjust sampling in received data intervals for optimal data reception by adjusting the phase of a data clock of a data sampler such a flash ADC. The device may also implement a second phase adjustment control loop with, for example, a baud-rate phase detector, that detects data intervals for further adjusting sampling at an optimal data time with the data sampler.

A receiver device implements enhanced data reception with edge-based clock and data recovery such as with a flash analog-to-digital converter architecture. In an example embodiment, the device implements a first phase adjustment control loop, with for example, a bang-bang phase detector, that detects data transitions for adjusting sampling at an optimal edge time with an edge sampler by adjusting a phase of an edge clock of the sampler. This loop may further adjust sampling in received data intervals for optimal data reception by adjusting the phase of a data clock of a data sampler such a flash ADC. The device may also implement a second phase adjustment control loop with, for example, a baud-rate phase detector, that detects data intervals for further adjusting sampling at an optimal data time with the data sampler.

Methods and systems for synchronizing at least one remote local oscillator with a central local oscillator, comprising receiving a remote local oscillator signal from at least one remote local oscillator and a master local oscillator signal from the central local oscillator and in response determining a round-trip phase measurement of temporal delay variability of the duplex real-time link between the remote station and central station, measuring frequency vs. time of the remote local oscillator signal relative to the master oscillator, adjusting the measured frequency vs. time according to the round-trip phase measurement to remove effects of temporal delay variability over the duplex real-time link telemetry, digitally filtering the measured frequency to remove variations in frequency on timescales<10? the round-trip delay and that are known not to be intrinsically due to the remote local oscillator, generating a phase increment signal from the filtered measured frequency, receiving and adjusting the local oscillator signal according to the phase increment signal and in response generating a derived digital domain clock signal that tracks the master local oscillator signal and converting the derived digital domain clock signal to an ultra-low phase-noise time domain voltage clock signal.

A receiver module includes a clock recovery circuit and a decision feedback equalizer (DFE) circuit. The DFE circuit includes a data feedback loop configured to sample an input data stream combined with equalization values based on a first clock signal. The DFE circuit also includes an edge feedback loop configured to sample the input data stream combined with equalization values based on a second clock signal. The clock recovery circuit is configured to determine a phase error between a receiver clock signal and a target clock signal based on output samples from the data feedback loop and the edge feedback loop.

A signal receiving apparatus includes a phase recovery look, a phase estimation circuit, a phase noise detection circuit, and a bandwidth setting circuit. The phase recovery loop performs a phase recovery process on an input signal according to a bandwidth setting. The phase estimation circuit generates an estimated phase associated with the input signal. The phase noise detection circuit determines a phase noise amount according to the estimated phase. The bandwidth setting circuit calculates an average and a variance of the phase noise amounts, and adjusts the bandwidth setting of the phase recovery loop according to the average and the variance.

A carrier frequency offset (CFO) tracking circuit includes: a CFO estimation circuit, generating an estimated CFO signal; a loop filter, coupled to the CFO estimation circuit, performing a loop filter operation on the estimated CFO signal according to an initial value to generate a loop filtered result; and an averaging circuit, coupled to the CFO estimation circuit and the loop filter, performing an average operation on the estimated CFO signal to generate the initial value as an average of the estimated CFO signal.

The present disclosure provides a symbol synchronization method and apparatus. By means of the symbol synchronization method and apparatus, a timing location is adjusted outside an adaptive loop. In addition, the adaptive loop proceeds to according to an original function of the adaptive loop. That is, the timing location is stabilized to an initial symbol-synchronization location, and the timing location is then further corrected and adjusted. Therefore, impact of an error of a timing location on symbol synchronization is eliminated by correcting the timing location, and positioning accuracy of a symbol-synchronization location is improved.

A receiver device implements enhanced data reception with edge-based clock and data recovery such as with a flash analog-to-digital converter architecture. In an example embodiment, the device implements a first phase adjustment control loop, with for example, a bang-bang phase detector, that detects data transitions for adjusting sampling at an optimal edge time with an edge sampler by adjusting a phase of an edge clock of the sampler. This loop may further adjust sampling in received data intervals for optimal data reception by adjusting the phase of a data clock of a data sampler such a flash ADC. The device may also implement a second phase adjustment control loop with, for example, a baud-rate phase detector, that detects data intervals for further adjusting sampling at an optimal data time with the data sampler.